Other Parts Discussed in Thread: DP83TC811
The current problem we encounter is that PHY chip DP83TC811RWRNDTQ1 cannot communicate with RGMII on the side of FPGA (MAC) :
(1) The SMI management bus from MAC to PHY is connected, and the register read and write is normal
(2) Loopback on the single MAC is passable
(3) The XMII loopback is blocked. Please refer to the attachment for the schematic diagram of the whole hardware
