DS90CF386: DS90CF386_C385A_setup_time_Value

Hi, 

Regardless of target PCLK, the same minimum limits will apply as what are called out in the datasheet. 

So the below values are still correct.

D.Fujiki said:

In DS90CF386 datasheet,
　Output SetupTime：Min　2ns　@85MHz
In DS90C385A datasheet,
　Input SetupTime：Min　2.5ns　＠85MHz

Regards, 

Logan

Hi, Logan
Thanks for your help.

Based on your answer, does that mean that TI's DS90CF386 and DS90C385A cannot be used as a pair?
I can understand that Input SetupTime: Min 2.5ns in DS90C385A is a fixed value regardless of PCLK.
However, I have a question about Output SetupTime:Min 2.0ns in DS90CF386.

For example, at 71.1MHz, the period is about 14ns.
If the Output SetupTime Min is 2.0ns, then the CLK will be shifted to the left side of the output waveform.
Please refer to the attached file for details.

DS90CF386_outputsetup_time_2ns.pdf

In design, in production and etc..., is there variation data of OutputSetupTime respect to PCLK in DS90CF386?
I want data as a below
-------
In DS90CF386,
　　１：　Please tell me the specification of Min output SetupTimeValue for 71.1MHz.
　　２：　Please tell me the specification of Min output SetupTimeValue for 51.2MHz.
-------

Best regards,

Hi D. 

Our forums will be down for maintenance through Monday of next week. I'm reviewing your question and will provide feedback when E2E support is resumed on Monday. Thanks for your patience. 

Regards, 

Logan 

Hi, Logan.

I am still expecting your response regarding this issue.

Best regards,

Thank you.