TFP410: VSYNC/HSYNC to DE assertion timing

Hi,

The timing information is covered in DVI spec section 3.4

Thanks

David

Thanks

I understand about blanking duration constraint. However, there is an additional check. Is the HSYNC/VSYNC assertion period at least 1 Tpixel, or do you need multiple cycles? If I want multiple cycles, do I have to follow VESA-CVT spec section 3.6?

Aizawa