SN65DP159: SN65DP159RGZ REview

Hi, John

Please see my feedback. 

1. Will the 5V on the be present on the SNK side?
   1. The source needs to provide the 5V HDMI power
2. How di I wire up the CEC pin from the connector?
   1. Is this a source or a dongle application? For source application, you can leave CEC_EN as NC. For dongle application, please refer to Fig 32 of the DP159 datasheet.

4812.SN65DP159_TI_Reviewed_10062022.pdf

Thanks

David

Hi David,

Thanks for the quick reply. Most appreciated.  The application is for a source. The TMDS streams are coming from an UltraScale Zynq GTH serdes with the SN65DP159 between the FPGA and the HDMI connector. I don't fully understand the difference between a regular source and a dongle but I'm assuming non-dongle application but I could be wrong.

Let me repharse my question regarding the SNK.  The DDC_CLK/DATA are pulled up to 5V between the HDMI connector and your IC.  On the FPGA side (SCL/SDA_SRC) is pulled up to 3.3V and goes to a 3.3V bank of the FPGA.  My question is will the 5V pullup voltage at the HDMI connector bleed through to the SRC pins and damage the 3.3V bank?  I don't know how the DDC block works internally with the I2C signals.

Thanks!!

John

John

he DDC_CLK/DATA are pulled up to 5V between the HDMI connector and your IC.  On the FPGA side (SCL/SDA_SRC) is pulled up to 3.3V and goes to a 3.3V bank of the FPGA.  My question is will the 5V pullup voltage at the HDMI connector bleed through to the SRC pins and damage the 3.3V bank?  I don't know how the DDC block works internally with the I2C signals.

You will not see the 5V on the sink side bleed to the source side. But since DP159 implements the clock stretching on its DDC bus, you need to make sure the FPGA can support clock stretching as well. Otherwise you will have to use an external level shifter and implement DDC snooping option.

Thanks

David