TFP410: VSYNC/HSYNC to DE assertion timing

kazuyuki aizawa

Part Number: TFP410

Is the HSYNC/VSYNC assertion period at least 1 Tpixel, or do you need multiple cycles? If I want multiple cycles, do I have to follow VESA-CVT spec section 3.6?

over 2 years ago

+1 Undrea Fields over 2 years ago

TI__Genius 11020 points

The HSYNC and VSYNC are output on one Tpixel boundaries during the blanking period(Multiple cycles are not required). The signals are latched on either rising or falling edge of IDCK.

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TFP410: VSYNC/HSYNC to DE assertion timing