DS90UB954-Q1: DS90UB954，DS90UB953

Hi Kailyn,

Thank you for your inquiry. I have a few questions which will help me to better understand this issue, could you please check with the customer on the below points?

• Do you have some additional details on the imager sensor that is being used here? We would need to know the horizontal active pixels, vertical active lines, total vertical lines, and frame rate.
• It looks like the setup for the DS90UB953 and DS90UB954 are provided here, could you please also get a register dump from the DS90UB954 for me to take a look at
• Could you also please confirm which form of forwarding you'd like to be using here? Is line interleave forwarding desired for this application?

Appreciate your help getting some feedback on these questions

Best,

Thomas

we use two ov2740,raw10,2lane,720Mbps/alne,1080p60 and two ti953 works at none sync mode,the ext osc is 50Mhz,STP cable;ti954  works at 1.6Gbps  and line interlaced， the ti954 can output two images,  the VC channel is 0x2b0 and 0x2b1, but it seems that the number of rows is insufficient, the number of columns is correct, ,Because it is fpga configured the ti953 and ti954, it is diffcult to  dump theregister information. the configuration is below :9'd0: i2c_data[23:0] <= {8'h32,8'h01 ,8'h03 }; //reset
9'd1: i2c_data[23:0] <= {8'h32,8'h02 ,8'h53 };
9'd2: i2c_data[23:0] <= {8'h32,8'h03 ,8'h02 }; /////non sync
9'd3: i2c_data[23:0] <= {8'h32,8'h05 ,8'h0b }; /////div
9'd4: i2c_data[23:0] <= {8'h32,8'h06 ,8'h66 };///////div
9'd5: i2c_data[23:0] <= {8'h32,8'h07 ,8'h7d }; //////div
9'd6: i2c_data[23:0] <= {8'h32,8'h33 ,8'h00 }; //////div   output 24M to sensor
/////////////////////////////////////////953_1////////////////////////////////////////////
9'd7: i2c_data[23:0] <= {8'h30,8'h01 ,8'h03 }; //reset
9'd8: i2c_data[23:0] <= {8'h30,8'h02 ,8'h53 };
9'd9: i2c_data[23:0] <= {8'h30,8'h03 ,8'h02 }; /////non sync
9'd10: i2c_data[23:0] <= {8'h30,8'h05 ,8'h0b }; /////div
9'd11: i2c_data[23:0] <= {8'h30,8'h06 ,8'h66 };///////div
9'd12: i2c_data[23:0] <= {8'h30,8'h07 ,8'h7d }; //////div
9'd13: i2c_data[23:0] <= {8'h30,8'h33 ,8'h00 }; //////div output 24M to sensor
/////////////////////////////////////////////954_PORT0//////////////////////////////////////////////////
9'd14: i2c_data[23:0] <= {8'h7A,8'h01 ,8'h03 };////reset
9'd15: i2c_data[23:0] <= {8'h7A,8'h4C ,8'h01 };
9'd16: i2c_data[23:0] <= {8'h7A,8'h70 ,8'h2B };
9'd17: i2c_data[23:0] <= {8'h7A,8'h72 ,8'h00 };
/////////////////////////////////////////////954_PORT1//////////////////////////////////////////////////
9'd18: i2c_data[23:0] <= {8'h7A,8'h4C ,8'h02 };
9'd19: i2c_data[23:0] <= {8'h7A,8'h72 ,8'h01 };
9'd20: i2c_data[23:0] <= {8'h7A,8'h70 ,8'h6B };
9'd21: i2c_data[23:0] <= {8'h7A,8'h1F ,8'h00 };
9'd22: i2c_data[23:0] <= {8'h7A,8'h20 ,8'h00 };
9'd23: i2c_data[23:0] <= {8'h7A,8'h6D ,8'h78 };
9'd24: i2c_data[23:0] <= {8'h7A,8'h33 ,8'h23 };
9'd25: i2c_data[23:0] <= {16'hffff ,8'hff };

thanks very much !!

Hi,

Would there be any way to get a register dump from these devices? There are a number of diagnostic registers in the 953 and 954 which are helpful to allow us to diagnose and resolve this issue.

Best,

Thomas

Can you give me some configration that others used correctly ?

you can tell me which reg i shoud pay attention and check ,Don't  around the question.

as if no refclk input  at ti954,how it can work at 1.6Gbps?  if it can work at 1.6Gbps, In CSI-2 non-synchronous clocking mode the DS90UB953-Q1 uses the CSI-2 clock for a reference. The
(CSI_CLK) the FPD-Link line rate is typically CSI_CLK × 10, FPD3_PCLK = 1/4 × CSI_CLK and back
channel rate is set to 10 Mbps. For example with CSI_CLK = 400 MHz, line rate = 4.0 Gbps, FPD3_PCLK =
100 MHz, the back channel data rate is 10 Mbps. When using the non-synchronous CSI-2 clocking mode, the
user must be certain the CSI-2 source meets the stringent jitter requirements for the serializer reference and
the CLK lane is always active. FPD-Link line rate equal 8Gbps ? 

thanks !!!

Hi,

It seems that there is some misunderstanding of the operating principles of the SER/DES devices here. The refclk on the DS90UB954 is not optional and is necessary for proper operation of the deserializer. In non-synchronous mode a oscillator is used to supply clock to the serializer and deserializer, where as in synchronous mode an oscillator is used on the deserializer as clock source, and the back channel from the deserializer is used as the clock source for the serializer. 

Do you have a schematic which you could provide for the DS90UB954 and DS90UB953 boards in this application? Before we dive into the register configuration of the serializer and deserializer we should confirm that the setup is correct from a hardware perspective.

Best,

Thomas

now  the ti954 can output two images,  the VC channel is 0x2b0 and 0x2b1,  when i set the reg of ti954 0x20 with 0x20 or 0x10,the output image is correct,when config 0x20 with 0x00,it seems that the number of each rows is insufficient, the number of columns is correct;so i would know:

1 : two sensors can  work freerun or  must sync ?

2: how dose ti954 merge the two image  to one ? if use line buffer it means the two sensors must work sync ?

Hi,

There are a number of CSI forwarding modes on the DS90UB954. These are described in the CSI-2 forwarding section of the datasheet and include best effort round robin forwarding (no sync needed), basic synchronized forwarding (sync needed), line-interleave forwarding (sync needed), and line-concatenated forwarding (sync needed). It sounds like the forwarding mode you referenced sounds like line-concatenating forwarding (which merges frames from two sensors into one) and requires synchronization of incoming video streams.

Best,

Thomas