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Original question:

DS125DF410: VCO locking range and VCO Cap DAC/LPF DAC VAL settings

DS125DF410: Higher than normal BER during bit transition

child sun
Prodigy 190 points

Part Number: DS125DF410

Hi TI Team,

We tried to plot the eye diagrams in heatmap format and noticed higher than normal BER during bit transition. It does not seem to make sense. Can you explain to us why this happens? Is it normal and expected?

Thanks.

Child

  • 0
    TI__Mastermind 19235 points

    Hi Child,

    Can you clarify how you are determining the heat map? Are you simply looking at the hit count? below for reference is the methodology suggested by TI.

    I'm not used to seeing the signature that you are observing when plotting the retimer input eye. This observation should be don't care though, as it is happening at high error region of the eye diagram anyways.

    Thanks,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 190 points

    Hi Rodrigo,

    I think we are talking about the same method, except that we have higher resolution for the color map. The color map from Table 53 may not show what we see, because any points with BER >1000 will be coded RED. Any idea? 

    Thanks.

    Child

  • 0 in reply to child sun
    TI__Mastermind 19235 points

    I believe this signature you are observing is a result of the retimer eye opening monitor (EOM) methodology. See EOM functional description below. The EOM comparators delta is max at the eye crossing. I think theoretically that is the result you would want see.

    • The EOM produces hit counts after sweeping across entire eye via adjustable phase and voltage offsets.
    • At each phase setting, the main comparator determines the nominal bit voltage value (for “0” or “1”)
    • The EOM also determines a bit value as detected by the offset comparator:
      • For each phase setting, the DAC is swept across the entire voltage range of the input signal
      • The offset comparator shifts the input data up/down per the reference DAC setting
      • The EOM logic determines the polarity of the signals at the outputs of the two comparator stages
      • When the bit polarity output by offset comparator is different than main comparator, the EOM logic  outputs a hit.
    • The number of hits is counted for the specified time interval at each setting of phase and voltage.
    • The resulting hit count map covering all phase and voltage offsets forms the 64 X 64 point eye diagram array.

    Regards,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 190 points

    Rodrigo,

    Thanks for the additional details of how the EOM works. However, by principle, the following two spots (A and B) should have the same bit error hits because their error rates should be 50% (half of the bits coming in are ONEs which are discriminated as ZEROs, as the threshold voltage of the comparator at A and B is high enough to make no difference in detected error rates)

    Is the chip spending the same amount of time to record bit error hits at A and B? If it happens to spend more time at A, we will see higher bit error hits at A. But is it the case?

    Thanks.

    Child

  • 0 in reply to child sun
    TI__Mastermind 19235 points

    Yes, EOM spends equal amount of time for areas A and B.

    Regards,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 190 points

    Rodrigo,

    Then what's the reason why area A has higher bit error hits?

    Child

  • 0 in reply to child sun
    TI__Mastermind 42018 points

    Hi Child,

    Please allow me to look into this question.  I can provide an update later today.

    Thanks,
    Drew

  • 0 in reply to Drew Miller1
    TI__Mastermind 42018 points

    Hi Child,

    After further investigation, I don't have a great explanation as to why area A has a higher hit count than area B.  With that said, is this impacting your ability to interpret data from the EOM?

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 190 points

    Drew,

    We do want to know why that happens because it seems to have revealed some internal issues and we would like to confirm if such an issue is predictable and limited (to certain conditions). Can your team dig deeper into the root cause?

    Thanks.

    Child

  • 0 in reply to child sun
    TI__Mastermind 42018 points

    Hi Child,

    I'm working with our team to look deeper into the root cause.  I can provide an update on Monday.

    Thanks,
    Drew

  • 0 in reply to Drew Miller1
    TI__Mastermind 42018 points

    Hi Child,

    I am still waiting to hear back from a teammate regarding the root cause of this.  I will update you later this week on this.

    Thanks,
    Drew