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Two DS90UB953 with DS90UB954 clock requirements

t gh
Prodigy 70 points
Other Parts Discussed in Thread: DS90UB953-Q1

we use two ov2740,raw10,2lane,720Mbps/alne,1080p60 and two ti953 works at none sync mode,the ext osc is 50Mhz,STP cable;ti954  works at 1.6Gbps  and line interlaced， the ti954 can output two images,  the VC channel is 0x2b0 and 0x2b1, but it seems that the number of rows is insufficient, the number of columns is correct,and when i set the reg of ti954 0x20 with 0x20 or 0x10,the output image is correct,when config 0x20 with 0x00,it seems that the number of rows is insufficient, the number of columns is correct;so i would know 

1 : two sensors can  work freerun or  must sync ?

2 : as  no refclk input  at ti954,how it can work at 1.6Gbps?  if it can work at 1.6Gbps, In CSI-2 non-synchronous clocking mode the DS90UB953-Q1 uses the CSI-2 clock for a reference. The
(CSI_CLK) the FPD-Link line rate is typically CSI_CLK × 10, FPD3_PCLK = 1/4 × CSI_CLK and back
channel rate is set to 10 Mbps. For example with CSI_CLK = 400 MHz, line rate = 4.0 Gbps, FPD3_PCLK =
100 MHz, the back channel data rate is 10 Mbps. When using the non-synchronous CSI-2 clocking mode, the
user must be certain the CSI-2 source meets the stringent jitter requirements for the serializer reference and
the CLK lane is always active. FPD-Link line rate equal 8Gbps ? 

3: how dose ti954 merge the two image  to one ? if use line buffer it means the two sensors must work sync ?

  • 0
    TI__Mastermind 26460 points

    Hello,

    Thank you for all the details about your system. It appears that this issue has two threads currently. In order to keep all information organized in one place can you keep all future responses and updates within this thread:

    e2e.ti.com/.../4372990

  • 0 in reply to Darrah Merillat
    Prodigy 70 points

    I want to rebuilt a new thread, because the other  thread has nothing help to me !!!

    thanks for understanding!!!

  • 0 in reply to t gh
    TI__Mastermind 26460 points

    Using the 954 without a refclk is not a valid use case for the devices. To successfully output the video data, the 954 requires a valid refclk otherwise the timing will not be correct. This set up may work occasionally, but it is not reliable or supported by the device specs. Please update your design to include refclk.


    In order to best support your issue, all information needs to remain in the original thread. Having all details and correspondence in one place will allow us to understand your system and find a solution. Please use the following thread for future communication related to this issue so we can offer support:

    e2e.ti.com/.../ds90ub954-q1-ds90ub954-ds90ub953

  • 0 in reply to Darrah Merillat
    Prodigy 70 points

    The figure is my design!!

    1 :  To successfully output the video data, the 954 requires a valid refclk otherwise the timing will not be correct.but in this figure,the 954 does't  connect a extent clock,this figure come from snla267a.pdf

    2  can you describe the detail difference between none syc and sync mode ？

    3： now i can output the merged image but the image seems not very veri veri stable 

  • 0 in reply to t gh
    TI__Mastermind 26460 points

    The figure in snla267 is demonstrating how the clocking scheme operates, it is not meant to be a schematic or block diagram. In the paragraph below this figure it states:

    "The second mode, non-synchronous CLK_IN, uses an external oscillator as a reference and generates the required clock for the FPD forward channel for that reference. Referring to Figure 5, the external clock must be fed into the CLK_IN pin (20) on the 953, running at a constant rate (f1) proportional to the REFCLK (f0), and a BC rate is then programmed to be less than or equal to 10 Mbps."

    Refclk is not used for the clocking scheme in nonsynchronous mode, but it is always required for the proper operation of the deserializer. There is no mode where a refclk is not required.

    There is no use going over registers, modes, or forwarding options to debug this system until there is a valid refclk. As long as there is no refclk on the 954 the system will not work. This is why your image is not stable.