• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 32 subscribers
  • Views 207 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

DS90UB948-Q1: test pattern generation with internal Clock

DS90UB948-Q1: Pattern generator | 0x65 PGCFG register

Shawn_Wang
Expert 3811 points
Part Number: DS90UB948-Q1
Other Parts Discussed in Thread: ALP

Hi team

I am confused on the DS90UB948-Q1 pattern generator setting: Application Note states "Write 0x03 to address 0x65 PGCFG" to enable the internal clock. But how to understand the 0x65[2] bit? This bit is related to video timing and "Write 0x03 to address 0x65 PGCFG" means the video timing is still from external. 

In addition, could you help give me the guidance on how to generate the pattern configuration code via APL?

I don't find a button on APL "Pattern generator" tab to generate the configuration code, and "Time Source" is also only fix to "Internal" and can not be changed to other option.

  • 0
    TI__Expert 4160 points

    Hi Shawn,

    Thank you for your question.

    Looking at the 0x65 register, you do not have to set 0x65 to 0x03 for internal clock. Internal timing/external timing is actually controlled in 0x65[3] bit. 0x65[3] is default to 0 which is already internal timing.

    I am pretty sure you are unable to set 948 to external timing because this is in demo mode and are not able to change register settings. There is no way to generate a configuration script in ALP for the 948. For 948 patgen configuration, simply enable 0x64[1] to enable patgen.

    Best Regards,

    William Y.