DS160PT801: Heat Sink Requirement

Bharath Muthukuri

Part Number: DS160PT801

Hello support,

I am studying DS160PT801 re-timer part for one of our applications and i will be loading the re-timer x4 lanes only. Die 0 or Die1.

Do i still need a Heat sink? any suggestions are appreciated.

As datasheet given maximum power numbers. Is there any power numbers for different speeds (or) each lane bifurcation x1, x2, x4, x8 etc.,

Thanks

Best Regards

over 3 years ago

+1 Nicholaus_Malone over 3 years ago

TI__Mastermind 27925 points

Hi Bharath,

I measured the power consumption for various link widths and datarates using our DS160PT801X16EVM. This is a small sample size, but maybe it will give you an idea of the power consumption you can expect.

DS160PT801_ProtocolPowerMeasurements.pdf

Regards,

Nicholaus

0 Bharath Muthukuri over 3 years ago in reply to Nicholaus_Malone

Prodigy 30 points

Hello Nicholaus,

Thank you for Power calculation sheet. It really helped.

I have one more question to clarify with you.

Do i need to terminate the unused Tx, Rx Port (Die0, Die1). In my case, I am using only Die1, Die need to be terminate or left floating? If termination is needed, How to terminate it? Please help me with a suggestion.

Thanks

Bharath Muthukuri

+1 Nicholaus_Malone over 3 years ago in reply to Bharath Muthukuri

TI__Mastermind 27925 points

Hi Bharath,

The Tx/Rx channels that are not being used should be left floating.

Regards,

Nicholaus

0 Bharath Muthukuri over 3 years ago in reply to Nicholaus_Malone

Prodigy 30 points

Hello Nicholaus,

Thank you your Response

For Re-timer EEPROM flashing, I see in EVK board re-timer is flashing through micro-controller.

Could you please recommend the tool (USB to SMbus) to connect to Sigcon Architect UI to DS160PT801 re-timer SMBus and flash.

Thanks

Bharath

+1 Nicholaus_Malone over 3 years ago in reply to Bharath Muthukuri

TI__Mastermind 27925 points

Hi Bharath,

If not using the EVM, then a USB2ANY should be used in order to use the SigCon Architect tool.

Regards,

Nicholaus

0 Bharath Muthukuri over 2 years ago in reply to Nicholaus_Malone

Prodigy 30 points

Hello Nicholaus,

Thank you for your quick response.

https://e2e.ti.com/user/conversations#New=True&UserId=312549

Above is the link of our one to one conversation link.

This is regarding Separate reference clocking architecture which we were discussing in our one to one conversation as shown in below snapshot.

We are in the layout phase of the design and considered TI re-timer chip in the below shown reference clock configuration.

Could you please confirm.

#1. Whether the TI Re-timer chip can be used in this configuration?

#2. Whether TI has validated this configuration in any of the root complexes and have results ?

#3. If #2 is not done then whether TI can support in validating this configuration in our setup if we face any challenges?

Thanks

Bharath

+1 Nicholaus_Malone over 2 years ago in reply to Bharath Muthukuri

TI__Mastermind 27925 points

Hi Bharath,

#1. No, the DS160PT801 datasheet states that it may not be used this way in the clocking architecture section.

#2. Yes, we have validated it with separate reference clock and have seen interop issues in enterprise applications; this is what led in the common-clock requirement in the DS160PT801 datasheet.

#3. I will provide support assuming that I have the equipment and hardware needed to help, but we would do so with the understanding that the datasheet is not being followed, and so we also would not be held responsible if the retimer does not work as described in the datasheet.

Regards,

Nicholaus

0 Bharath Muthukuri over 2 years ago in reply to Nicholaus_Malone

Prodigy 30 points

Hello Nicholaus,

This is regarding Differential pair length matching.

As I see in datasheet, there are package length matching details in table 11-1, 11-2, 11-3 and 11-4.

Do you have any recommendations for overall trace length, length matching and time delay for differential signal pairs. Please help to share.

Thank you

Bharath Muthukuri

0 Nicholaus_Malone over 2 years ago in reply to Bharath Muthukuri

TI__Mastermind 27925 points

Hi Bharath,

Yes, we have recommendations in the following documents.

High-Speed Layout Guidelines for Signal Conditioners and USB Hubs (Section 2.5)

High-Speed Interface Layout Guidelines (Rev. I) (ti.com) (Section 3)

PCIe has a de-skew process built in that makes it very tolerant to variances in trace lengths, overall trace length is limited by the loss budget (28dB at Gen4), time delay is not relevant for high-speed PCIe signals.

Regards,

Nicholaus

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DS160PT801: Heat Sink Requirement