TLK6002: Not able to understand "ARS State Machine Flowchart", Please provide step by step procedure for ARS mode

Hi Mallikarjuna,

Apologies for the delay.  The state machine flowchart is not very explicit, but I think through some inferences, we can address these questions.  Reading the flowchart, it seems like we want to end up at the "ARS Locked State".  The state machine basically remains there as long as sync is maintained.

In order to reach this state, we must pass through the "Drive ENPLL Low" state and ">=16?", "PLL Lock?" conditions.  It's worth noting that the state machine only continues past these blocks if PLL is not locked.  I believe the purpose of these 3 blocks is to protect against a false lock scenario.  If the previously attempted bit rate resulted in lock, but not synchronization, it might be important to unlock and relock the PLL after changing SERDES settings.

The inference I believe we must make is that once the "Wait for PLL Lock" state is reached, I believe ENPLL is driven high.  The "Wait for PLL Lock" and two conditional checks following it seem dedicated to achieving PLL lock.

To directly answer your questions:

Q1: If ENPLL Low then how PLL will lock?

A1: PLL should not lock while ENPLL is low. Driving ENPLL high is not explicitly shown in flowchart, but I believe it occurs at the "Wait for PLL Lock" state.

Q2: When PLL is locked for first time again driving ENPLL to Low and checking for PLL lock but if PLL locked for second time then going to next step?

A2: PLL must be unlocked to reach the "Wait for PLL Lock" state in the state machine.

Thanks,
Drew

Hi Mallikarjuna,

I would expect that the state machine would handle this automatically.

Thanks,
Drew