DP83825I: Ethernet IC Configuration

Hi Rishav,

Please let me provide the feedback on the schematic by Tuesday next week.

Here are some documents on RMII https://www.ti.com/lit/an/snla076a/snla076a.pdf https://www.ti.com/lit/an/snla101a/snla101a.pdf

--
Regards,
Gokul.

Thanks for your response and we will wait for your inputs. Same time just to be more specific on our queries with this, here I add below few questions  

- Common clock source we have used (50MHz oscillator 'ASE-50.000MHZ-LR-T' from Abracon) to feed PHY XI pin as well as microcontroller's 'ETH_CLK'. Please suggest if there is any issue / specific thing to be taken care with this arrangement.

- For 'RST_N' we have assigned microcontroller's dedicated pin can operate in GPIO mode incase need to reset the PHY. Hope this is OK

- Does TI offer any support / share firmware example routine which we can easily implement in our host microcontroller to manage/configure this PHY?

Hi Rishav,

I will check with my team if there is a sample linux code which we can share with you.

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Regards,
Gokul.

Hi Rishav,

You can find the sample linux code here https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/phy/dp83822.c

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Regards,
Gokul.

Hi Gokul, 

Just follow up on hardware and other queries. Mention code driver noted well and will refer

Hi Gokul, 

Request you to please answer our Hardware queries ASAP so that we can accommodate the changes if any in our design.

Thanks, 

Rishav 

Hi Rishav,

PFA, the schematic with annotated comments. The schematic mostly looks good.

Ethernet review_feedback.pdf

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Regards,
Gokul.

Also, Please respond to the queries before we freeze the hardware 

Common clock source we have used (50MHz oscillator 'ASE-50.000MHZ-LR-T' from Abracon) to feed PHY XI pin as well as microcontroller's 'ETH_CLK'. Please suggest if there is any issue / specific thing to be taken care with this arrangement.