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Original question:

DS90UB960-Q1: DS90UB960-Q1: Des Register Settings & Clarification

DS90UB960-Q1: DS90ub960 - Test pattern generation

Blessy Abraham
Prodigy 50 points
Part Number: DS90UB960-Q1

Hi Team, 

We are using the deserializer ds90ub960 to generate a test pattern. We are NOT able to capture the test pattern. We see that the v4l2-ctl is waiting for the frame and it is not getting any frame.


While waiting, if we do a digital_reset0 (0x01 = 0x01), we see the capture of test-pattern happening. Otherwise, the capture wouldn't happen 

Can you let us know why this is happening? 

  • 0
    TI__Mastermind 26750 points

    Hello,

    Are you saying that the pattern generator only works after you do a digital reset on the 960? Could you provide the script you are using?

    Regards,

    Darrah

  • +1 in reply to Darrah Merillat
    Prodigy 50 points

    Hi Darrah, 

    An update regarding the issue. We are now able to capture the test pattern after we disabled the CSI-2 continuous clock-mode in the CSI_CTL Register (Address 0x33). 0x33 = 0x21.

    Can you give us the information on what is the difference between the CSI-2 continuous clock-mode and non-continuous clock-mode?

    Providing you the below configuration that we are using.

    write_reg(0x01, 0x03);
    write_reg(DS90UB_SR_CSI_PLL_CTL, 0x02);
    write_reg(DS90UB_SR_FWD_CTL2, 0x03);
    write_reg(DS90UB_TR_CSI_PORT_SEL, 0x01);
    write_reg(DS90UB_TR_CSI_CTL, 0x21); ----------------------------------> this resolved the issue. This was previously 0x23.
    write_reg(DS90UB_SR_GEN_CONFIG, 0x3E);
    write_reg(DS90UB_SR_SCL_HIGH_TIME, 0x06);
    write_reg(DS90UB_SR_SCL_LOW_TIME, 0x0C);

    write_reg(DS90UB_SR_FPD3_PORT_SEL, 0x00);
    write_reg(0x58, 0x5E);
    write_reg(DS90UB_SR_INTERRUPT_CTL, 0x8F);
    write_reg(DS90UB_RR_PORT_ICR_LO, 0x01);
    write_reg(0x5C, 0x22);
    write_reg(0x5D, 0x20);
    write_reg(0x65, 0x12);

    write_reg(DS90UB_SR_RX_PORT_CTL, 0x0F);
    write_reg(DS90UB_SR_FWD_CTL1, 0x00);
    write_reg(DS90UB_SR_FWD_CTL2, 0x43);
    write_reg(DS90UB_TR_CSI_PORT_SEL, 0x01);
    write_reg(DS90UB_SR_INTERRUPT_CTL, 0x8F);


    Test Pattern

    write_reg(DS90UB_SR_FWD_CTL1, 0xF0);
    write_reg(DS90UB_SR_IND_ACC_CTL, DS90UB_SR_IND_ACC_CTL_IA_AUTO_INC | 0);
    write_ind8(DS90UB_IR_PGEN_CTL, DS90UB_IR_PGEN_CTL_PGEN_ENABLE);
    write_ind8(DS90UB_IR_PGEN_CFG, 0x83);
    write_ind8(DS90UB_IR_PGEN_CSI_DI, 0x24);
    write_ind16(DS90UB_IR_PGEN_LINE_SIZE1, 0x1E00);
    write_ind16(DS90UB_IR_PGEN_BAR_SIZE1, 0x1E00);
    write_ind16(DS90UB_IR_PGEN_ACT_LPF1, 0x0320);
    write_ind16(DS90UB_IR_PGEN_TOT_LPF1, 0x046A);
    write_ind16(DS90UB_IR_PGEN_LINE_PD1, 0x05C3);
    write_ind8(DS90UB_IR_PGEN_VBP, 0x21);
    write_ind8(DS90UB_IR_PGEN_VFP, 0x0A);

  • 0 in reply to Blessy Abraham
    TI__Mastermind 26750 points

    The distinction between continuous and non-continuous clock comes from the mipi standard and is not specific to the ds90ub devices. In continuous clock mode the clock lanes will continue to generate clock signals even in between the transmission of data packets and in non-continuous mode the clock lanes will enter a low power state in between data packets resulting in a non-continuous clock signal. The imager, SOC, processor, or other device in your system probably requires this specific type of clocking configuration.