HD3SS3212-Q1: HD3SS3212RKSRQ1

B port is type-A connector.

C port is SOC

what is A port connected to?

AC cap is need d only on one side on TX, so CAP2105/2106 can be removed.

Regadrs

Brian

Hi Brian:

   A port is connect to Quectel 5G SoC USB 3.0 interface .

 How about A port CAP2107 and CAP2108 can be remove since there already have place on Tx side.

thank you

You can place AC capon one side of TX lane, either on A port or B/C port.

Regadsr

brian

Hi Brian:

   Thank you for your suggestion. Let me update again customer design HD3SS3212-Q1 schematic on the attachment. 

here is application block diagram: 

Application :  USB3.0

 AG550Q : Host 

AG215S: Device

USB Type A connect to Laptop : Device

Could you double check schematic design have any suggestion? thank you

Heron_P1_TI_USB SW_230103.pdf

what is purpose of co-layout? AC cap is needed for USB TX lane.

Hi Brian:

  It's just reserve for testing. I will update place AC cap on the both Tx side. 

thanks  

Roy:

   AC cap is needed only on one side of Mux.

Regards

Brian

Hi Brian:

   Thank you for your suggestion. here is the latest schematic update from customer. 

The major High speed USB signal communication is come from USB Type A Port. AG215S is only reserve. for debugging. AG550Q is Host.

So the Schematic CAP2109. CAP2110 , CAP2105, CAP2106 were NC. (HD3SS3212 B0 and B1 is NC) .

C0 and C1 is active signal USB Type A 3.0 protocol . could you please help double check the schematic have any  problems .

Sorry , Schematic is attachment .4848.Heron_P1_TI_USB SW_230103.pdf

4848.Heron_P1_TI_USB SW_230103.pdf