Other Parts Discussed in Thread: DP83869
Hello,
We have some problems with the Ethernet Phy DP83869HM after Power-Up.
Our Configuration:
- Three Supply Mode is used (The Power up Sequence looks good)
- IO Voltage is 1V8
- We want to use the Phy in RGMII to Copper Mode.
- 25MHz Oscillator is used (clk_out pin always shows a 25MHz Signal)
- Reset Signal comes from a FPGA and meets the timing constrains.
- Bootstrap Mode is SGMII to Copper - we want to reconifigure the Phy per Software/MDIO to RGMII to Copper Mode
Problem:
Sometimes it seems that the Phy is not correct come up. (2 from 10 times)
We can not access the Phy via MDIO Interface.
Under what circumstances will the Interface be disabled?
It seems that the mode is strap incorrectly.
In the event of an error, we assume that the device is in boundary scan mode or in an invalid mode.
What is the behavoir in Boundary Scan Mode?
- Is the MDIO Interface still active?
- Is the Reset Input Pin active?
- Is the clk_out Pin active?
The PHYIDR2 Register on our devices is 0xA0F1. We expect 0xA0F3.
What are the differnces between revision number 1 and 3?
Page 96 of the datasheet says:
"The strap (SUPPLYMODE_SEL, pin 23) shall be pulled low to set double supply mode. VDDIO may be 3.3 V, 2.5 V, or 1.8 V. VDDIO_SEL strap shall be selected appropriately to VDDIO voltage applied"
We can't find further information about the SUPPLYMODE_SEL and the VDDIO_SEL strap.
Regards,
Dominik
