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SN65DSI86-Q1: panel node error for DP via dsi bridge

Part Number: SN65DSI86-Q1
Other Parts Discussed in Thread: SN65DSI86, SN65DSI86EVM

Hi,

we are trying to bringUp the same bridge (via imx8MP hummingbird EVB by solidrun)

we have attached a DELL P2720D DP display to the bridge's EVB using the standard onboard port.

and have been receiving the same error:

Jan 19 13:26:56 imx8mpsolidrun kernel: [drm:ti_sn_bridge_probe [ti_sn65dsi86]] *ERROR* could not find any panel node

note that i2c communications are working fine and we also tried disabling the ASSR and enabling the color bar (
nothing was visible on the display)

please find the attached DTS and boot log.

any help will be appreciated,

Thanks.

5758.boot.log

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 */

/dts-v1/;
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/usb/pd.h>

#include "imx8mp-sr-som.dtsi"

/ {
	model = "SolidRun i.MX8MP HummingBoard Pulse";
	compatible = "fsl,imx8mp-sr-som", "fsl,imx8mp";

	leds {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_led>;

		/*status {
			label = "status";
			gpios = <&gpio4 22 0>;
			default-state = "on";
		};*/
	};

	power-m2-mpcie {
        	compatible = "reg-userspace-consumer";
        	regulator-name = "m2-mpcie-pwr-consumer";
		regulator-boot-on;
		regulator-supplies = "vcc";
        	vcc-supply = <&reg_m2_mpcie_pwr>;
        	comment = "m.2 and mpcie 3.3V connector switch";
    	};

	power-usb-port1 {
        	compatible = "reg-userspace-consumer";
        	regulator-name = "usb-port1-pwr-consumer";
		regulator-boot-on;
		regulator-supplies = "vcc";
        	vcc-supply = <&reg_usb1_host_vbus>;
        	comment = "USB Port1 vbus power switch";
    	};

	power-usb-port2 {
        	compatible = "reg-userspace-consumer";
        	regulator-name = "usb-port2-pwr-consumer";
		regulator-boot-on;
		regulator-supplies = "vcc";
        	vcc-supply = <&reg_usb1_vbus>;
        	comment = "USB Port2 vbus power switch";
    	};

	reg_m2_mpcie_pwr: regulator-m2-mpcie-pwr {
		compatible = "regulator-fixed";
		regulator-name = "m2-mpcie-pwr";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_m2_pwr>;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usb1_host_vbus: regulator-usb1-host-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb1_host_vbus";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb1_host_vbus>;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usb1_vbus: regulator-usb1-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb1_vbus";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb1_vbus>;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_LOW>;
		regulator-always-on;
	};

	reg_vdd_1v8: regulator-vdd-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "VDD_1V8";
                vdd-3v3-supply = <&buck4>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
	};

	rfkill_m2_wdis {
		compatible = "rfkill-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_m2_rfkill>;
		rfkill-name = "m2_wdis";
		rfkill-type = <5>;
		reset-gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
		shutdown-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
		status = "okay";
	};

	rfkill_m2_gps {
		compatible = "rfkill-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_m2_gps_rfkill>;
		rfkill-name = "m2_gps";
		rfkill-type = <6>;
		shutdown-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
		status = "okay";
	};

	rfkill_mpcie_wdis {
		compatible = "rfkill-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mpcie_rfkill>;
		rfkill-name = "mpcie_wdis";
		rfkill-type = <5>;
		reset-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
		shutdown-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
		status = "okay";
	};

	sound-hdmi {
		compatible = "fsl,imx-audio-cdnhdmi";
		model = "audio-hdmi";
		audio-cpu = <&aud2htx>;
		hdmi-out;
		constraint-rate = <44100>,
				<88200>,
				<176400>,
				<32000>,
				<48000>,
				<96000>,
				<192000>;
		status = "disabled";
	};

	sound-wm8904 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "wm8904-audio";
		simple-audio-card,format = "i2s";
		simple-audio-card,frame-master = <&sound_wm8904_cpu>;
		simple-audio-card,bitclock-master = <&sound_wm8904_cpu>;
		simple-audio-card,widgets =
			"Headphone", "Headphone Jack",
			"Microphone", "Headset Microphone";
		simple-audio-card,routing =
			"Headphone Jack", "HPOUTL",
			"Headphone Jack", "HPOUTR",
			"Headset Microphone", "MICBIAS",
			"IN2R", "Headset Microphone";

		sound_wm8904_cpu: simple-audio-card,cpu {
			sound-dai = <&sai3>;
			dai-tdm-slot-num = <2>;
			dai-tdm-slot-width = <32>;
		};

		sound_wm8904_codec: simple-audio-card,codec {
			sound-dai = <&wm8904>;
		};
	};
	
	sn65dsi86_refclk: sn65dsi86-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;

		clock-frequency = <27000000>;
	};

	backlight: backlight {
		compatible = "pwm-backlight";
//		pwms = <&dsi_2_edp_bridge 1000000>;
//		enable-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
	};	


	dsi_2_edp_en: dsi-2-edp-en {
		pinmux {
			pins = "gpio102";
			function = "gpio";
		};

		pinconf {
			pins = "gpio102";
			drive-strength = <2>;
			bias-disable;
		};
	};

	dsi_2_edp_irq: dsi-2-edp-irq {
		pinmux {
			pins = "gpio10";
			function = "gpio";
		};

		pinconf {
			pins = "gpio10";
			drive-strength = <2>;
			bias-pull-down;
		};
	};
	
	/*panel: panel {
		compatible = "simple-panel", "qcom,sc7180-dp";
		//backlight = <&backlight>;
		panel-width-mm = <2560>;
		panel-height-mm = <1440>;
		status = "okay";

		no-hpd;		

		port {
			panel_in_edp: endpoint {
				remote-endpoint = <&sn65dsi86_out>;
			};
		};
	};*/

};

&aud2htx {
	status = "okay";
};

&basler_1 {
        status = "okay";
};

&easrc {
	fsl,asrc-rate  = <48000>;
	status = "okay";
};

&ecspi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	fsl,spi-num-chipselects = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
	status = "okay";

	spidev1: spi@0 {
		reg = <0>;
		compatible = "linux,spidev";
		spi-max-frequency = <10000000>;
	};
};

/*eth0*/
&eqos {
	status = "okay";
};

&flexspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	status = "okay";
};


&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	/*sound codec*/
	wm8904: codec@1a {
		#sound-dai-cells = <0>;
		compatible = "cirrus,wm8904", "wlf,wm8904";
		reg = <0x1a>;
		DBVDD-supply = <&buck4>;
		MICVDD-supply = <&buck4>;
		DCVDD-supply = <&reg_vdd_1v8>;
		AVDD-supply = <&reg_vdd_1v8>;
		CPVDD-supply = <&reg_vdd_1v8>;
		clocks = <&clk IMX8MP_CLK_SAI3>;
		clock-names = "mclk";
		status = "okay";
	};
};

&i2c3 {
        #address-cells = <1>;
        #size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	basler_0: basler_camera_vvcam@36 {
		compatible = "basler,basler-camera-vvcam", "basler-camera-vvcam";
		reg = <0x36>;
		csi_id = <0x00>;
		status = "okay";

		port {
			basler_ep_0: endpoint {
				data-lanes = <1 2 3 4>;
				clock-lanes = <0>;
				link-frequencies = /bits/ 64 <750000000>;

				max-lane-frequency = /bits/ 64 <750000000>;
				max-pixel-frequency = /bits/ 64 <266000000>;
				max-data-rate = /bits/ 64 <0>;

				remote-endpoint = <&mipi_csi0_ep>;
			};
		};
	};

	adv_bridge: adv7535@3d {
		compatible = "adi,adv7533";
		reg = <0x3d>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mipi_dsi_en>;
		adi,addr-cec = <0x3c>;
		adi,addr-edid = <0x3b>;
		adi,dsi-lanes = <4>;
		gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
		status = "disabled";


		/*port {
			adv7535_from_dsim: endpoint {
				remote-endpoint = <&dsim_to_adv7535>;
			};
		};*/
	};

	eeprom_carrier: eeprom@57 {
		compatible = "st,24c02", "atmel,24c02";
		reg = <0x57>;
		pagesize = <8>;
	};

	rtc: rtc@69 {
		compatible = "abracon,ab1805";
		reg = <0x69>;
		abracon,tc-diode = "schottky";
		abracon,tc-resistor = <3>;
	};

	dsi_2_edp_bridge: sn65dsi86@2d {
		compatible = "ti,sn65dsi86";
		reg = <0x2d>;

		ti,dsi-lanes = <4>;
		max,dsi-channel = <1>;
		ti,dp-lanes = <4>;
		pinctrl-names = "default";
		
//		pinctrl-0 = <&dsi_2_edp_en>, <&dsi_2_edp_irq>;
		
//		gpio-controller;
		#gpio-cells = <2>;
		
		//interrupt-parent = <&tlmm>;
//		interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;

		//enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>;

		/*vpll-supply = <&src_pp1800_s4a>;
		vccio-supply = <&src_pp1800_s4a>;
		vcca-supply = <&src_pp1200_l2a>;
		vcc-supply = <&src_pp1200_l2a>;
		*/

		//clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
		clocks = <&sn65dsi86_refclk>;
		clock-names = "refclk";
		no-hpd;

		panel@0 {
			compatible = ""panel-simple";  // edp
			reg = <0>;
			pinctrl-0 = <&pinctrl_mipi_dsi_en>;
			// reset-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
			enable-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
			panel-width-mm = <256>;
			panel-height-mm = <144>;
			// backlight = <&backlight>;
			port {
				panel_in_edp: endpoint {
					remote-endpoint = <&sn65dsi86_out>;
				};
			};
		};

		ports {
			port@1 {
				reg = <1>;
				sn65dsi86_in: endpoint {
					remote-endpoint = <&dsi0_out>;
				};
			};

			port@2 {
				reg = <2>;
				sn65dsi86_out: endpoint {
					remote-endpoint = <&panel_in_edp>;
				};
			};
		};
	};
};
			
&irqsteer_hdmi {
	status = "okay";
};

&hdmi {
	status = "okay";
};

&hdmi_blk_ctrl {
	status = "okay";
};

&hdmi_pavi {
	status = "okay";
};

&hdmiphy {
	status = "okay";
};

&isp_0 {
	status = "okay";
};

&isp_1 {
	status = "okay";
};

/*micro HDMI*/
&lcdif1 {
	status = "okay";
};

&lcdif2 {
	status = "disabled";
};

/*HDMI*/
&lcdif3 {
	status = "disabled";
};

&micfil {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pdm>;
	assigned-clocks = <&clk IMX8MP_CLK_PDM>;
	assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <196608000>;
	status = "disabled";
};

&mipi_csi_0 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <266000000>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
	assigned-clock-rates = <266000000>;
	status = "okay";

	port@0 {
		reg = <0>;
		mipi_csi0_ep: endpoint {
			remote-endpoint = <&basler_ep_0>;
			data-lanes = <4>;
			csis-hs-settle = <16>;
		};
	};

};

&mipi_csi_1 {
	status = "okay";
};

&mipi_dsi {
	status = "okay";
        //compatible = "fsl,imx8mp-mipi-dsim";

	port@1 {
		dsi0_out: endpoint {
			remote-endpoint = <&sn65dsi86_in>;
			attach-bridge;
		};
	};
		
	/*port@1 {
		dsim_to_adv7535: endpoint {
			remote-endpoint = <&adv7535_from_dsim>;
			attach-bridge;
		};
	};*/
};

&pcie{
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	reset-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>;
	ext_osc = <0>;
	clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
		 <&clk IMX8MP_CLK_PCIE_AUX>,
		 <&clk IMX8MP_CLK_HSIO_AXI>,
		 <&clk IMX8MP_CLK_PCIE_ROOT>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
			  <&clk IMX8MP_CLK_PCIE_AUX>;
	assigned-clock-rates = <500000000>, <10000000>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
				 <&clk IMX8MP_SYS_PLL2_50M>;
	status = "okay";
};

&pcie_phy{
	ext_osc = <0>;
	status = "okay";
};

&pwm4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm4>;
	status = "okay";
};

&sai3 {
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai3>;
        assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
        assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
        assigned-clock-rates = <12288000>;
        clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>,
                 <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
                 <&clk IMX8MP_CLK_DUMMY>;
        clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
        fsl,sai-mclk-direction-output;
	status = "okay";
};

&sdma2 {
        status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	assigned-clocks = <&clk IMX8MP_CLK_UART3>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&usb3_phy0 {
	fsl,phy-tx-preemp-amp-tune = <2>;
	status = "okay";
};

&usb3_0 {
	status = "okay";
};

&usb_dwc3_0 {
	dr_mode = "host";
	status = "okay";
};

&usb3_phy1 {
	fsl,phy-tx-preemp-amp-tune = <2>;
	status = "okay";
};

&usb3_1 {
	status = "okay";
};

&usb_dwc3_1 {
	dr_mode = "host";
	snps,parkmode-disable-ss-quirk;
	status = "okay";
};

&usdhc2 {
	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	voltage-ranges = <1800 1800 3300 3300>;
	bus-width = <4>;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;


	/*pinctrl_edp_mux: kzmuxedpgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28		0x01
		>;
	};*/
	
	pinctrl_ecspi2: ecspi2grp {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK		0x82
			MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI		0x82
			MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO		0x82
		>;
	};

	pinctrl_ecspi2_cs: ecspi2cs {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13		0x40000
		>;
	};

	pinctrl_gpio_led: gpioledgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22		0x19
			MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21		0x19
			MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23		0x19
			MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24		0x19
			MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28		0x19
		>;
	};

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c3
			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x400001c3
			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x40000019
			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x40000019
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL			0x400001c3
			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA			0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x400001c3
			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x400001c3
		>;
	};

	pinctrl_flexspi0: flexspi0grp {
		fsl,pins = <
			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2
			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82
			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82
			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82
			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82
		>;
	};

	pinctrl_m2_rfkill: m2_rfkill_grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06		0x19
			MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13		0x19
		>;
	};

	pinctrl_m2_gps_rfkill: m2_gps_rfkill_grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07		0x19
		>;
	};

	pinctrl_m2_pwr: mp2_pwr_grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10		0x19
		>;
	};

	pinctrl_mpcie_rfkill: mpcie_rfkill_grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01		0x19
			MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05		0x19
		>;
	};

	pinctrl_mipi_dsi_en: mipi_dsi_en {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08		0x16
		>;
	};

        pinctrl_pcie: pciegrp {
                fsl,pins = <
                        MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x41/*pcie reset*/
                >;
        };

	pinctrl_pdm: pdmgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK			0xd6
			MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00	0xd6
			MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01	0xd6
			MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02	0xd6
			MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03	0xd6
		>;
	};

	pinctrl_pwm4: pwm4grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT		0x116
		>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19		0x40
		>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK	0xd6
			MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC	0xd6
			MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK	0xd6
			MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00	0xd6
			MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00	0xd6
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX		0x140
			MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX		0x140
			MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS		0x140
			MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS		0x140
		>;
	};

	pinctrl_usb1_host_vbus: usb1hostgrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14		0x19
		>;
	};

	pinctrl_usb1_vbus: usb1grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15		0x19
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x190
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d0
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d0
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d0
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d0
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d0
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT		0xc1
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x194
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d4
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d4
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d4
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d4
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d4
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 	0xc1
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK		0x196
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD		0x1d6
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0		0x1d6
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1		0x1d6
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2		0x1d6
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3		0x1d6
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 	0xc1
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2grp-gpio {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 		0x1c4
		>;
	};
};

  • the bridge's evm being used - SN65DSI86EVM - www.ti.com/.../SN65DSI86EVM  

  • Hello, Shlomi, 

    How is this device's register being written to and to what values?

    There is an excel sheet that you can use found in this link:

    https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945404/faq-sn65dsi86-how-do-i-programming-the-sn65dsi86-registers.

    Also, have you tried reading from the error registers F0 - F8? Do those return any errors?

    Thanks,

    Zach

  • Hi,

    the edid values I've input to the excel (got it when connected the display to another machine via HDMI port):


    00 ff ff ff ff ff ff 00 10 ac 01 d1 4c 33 54 30
    34 1e 01 03 80 3c 22 78 ea 4c 55 a9 55 4d 9d 26
    0f 50 54 a5 4b 00 81 00 b3 00 d1 00 71 4f a9 40
    81 80 d1 c0 01 01 56 5e 00 a0 a0 a0 29 50 30 20
    35 00 55 50 21 00 00 1a 00 00 00 ff 00 46 5a 4d
    39 36 34 33 0a 20 20 20 20 20 00 00 00 fc 00 44
    45 4c 4c 20 50 32 37 32 30 44 0a 20 00 00 00 fd
    00 31 4b 1d 71 1c 00 0a 20 20 20 20 20 20 01 b9

    before loading the kernel module (ti-sn65dsi86.ko) im setting the registers in this manner (extracted from the ASSR excel script):

    i2cset -y 2 0x2d 0x0a 0x06
    i2cset -y 2 0x2d 0x10 0x26
    i2cset -y 2 0x2d 0x12 0x6c

    i2cset -y 2 0x2d 0x94 0x80

    i2cset -y 2 0x2d 0x0d 0x01
    i2cset -y 2 0x2d 0x64 0x01
    i2cset -y 2 0x2d 0x74 0x00
    i2cset -y 2 0x2d 0x01 0x0a
    i2cset -y 2 0x2d 0x01 0x81
    i2cset -y 2 0x2d 0x5a 0x05

    the noASSR script gives a lot of uncalculated values:

    <aardvark>        
    <configure i2c="1" spi="1" gpio="0" tpower="1" pullups="0"/>        
    <i2c_bitrate khz="100"/>        
             
    ======ASSR RW control ======
    <i2c_write addr="0x2D" count="1" radix="16"> FF 7 </i2c_write>/>  
    <i2c_write addr="0x2D" count="1" radix="16"> 16 1 </i2c_write>/>  
    <i2c_write addr="0x2D" count="1" radix="16"> FF 0 </i2c_write>/>  
             
    ======REFCLK Frequency ======
    <i2c_write addr="0x2D" count="1" radix="16"> 0A 6 </i2c_write>/>  
             
    ======DSI Mode ======
    <i2c_write addr="0x2D" count="1" radix="16"> 10 26 </i2c_write>/>  
             
    ======DSIA Clock ======
    <i2c_write addr="0x2D" count="1" radix="16"> 12 6C </i2c_write>/>  
             
    ======DSIB Clock ======
    <i2c_write addr="0x2D" count="1" radix="16"> 13 6C </i2c_write>/>  
             
    ======DP Datarate ======
    <i2c_write addr="0x2D" count="1" radix="16"> 94 #VALUE! </i2c_write>/>  
             
    ======Enable PLL ======
    <i2c_write addr="0x2D" count="1" radix="16"> 0D 1 </i2c_write> <sleep ms="10"/>  
             
    ======Enable enhanced frame in DSI86 ======
    <i2c_write addr="0x2D" count="1" radix="16"> 5A 4 </i2c_write>/>  
             
    ======Number of DP lanes ======
    <i2c_write addr="0x2D" count="1" radix="16"> 93 #VALUE! </i2c_write>/>  
             
    ======Start Semi-Auto Link Training ======
    <i2c_write addr="0x2D" count="1" radix="16"> 96 0A </i2c_write> <sleep ms="20"/>  
             
    ======CHA Active Line Length ======
    <i2c_write addr="0x2D" count="2" radix="16"> 20 #VALUE! #VALUE! </i2c_write>/>
             
    ======CHB Active Line Length ======
    <i2c_write addr="0x2D" count="2" radix="16"> 22 0 0 </i2c_write>/>
             
    ======Vertical Active Size ======
    <i2c_write addr="0x2D" count="2" radix="16"> 24 #VALUE! #VALUE! </i2c_write>/>
             
    ======Horizontal Pulse Width ======
    <i2c_write addr="0x2D" count="2" radix="16"> 2C #VALUE! #VALUE! </i2c_write>/>
             
    ======Vertical Pulse Width ======
    <i2c_write addr="0x2D" count="2" radix="16"> 30 #VALUE! #VALUE! </i2c_write>/>
             
    ======HBP ======
    <i2c_write addr="0x2D" count="1" radix="16"> 34 #VALUE! </i2c_write>/>  
             
    ======VBP ======
    <i2c_write addr="0x2D" count="1" radix="16"> 36 #VALUE! </i2c_write>/>  
             
    ===== HFP ======
    <i2c_write addr="0x2D" count="1" radix="16"> 38 #VALUE! </i2c_write>/>  
             
    ===== VFP ======
    <i2c_write addr="0x2D" count="1" radix="16"> 3A #VALUE! </i2c_write>/>  
             
    ===== DP-18BPP Disable ======
    <i2c_write addr="0x2D" count="1" radix="16"> 5B 0 </i2c_write>/>  
             
    ===== Color Bar Enable ======
    <i2c_write addr="0x2D" count="1" radix="16"> 3C 12 </i2c_write>/>  
             
    ===== Enhanced Frame, and Vstream Enable ======
    <i2c_write addr="0x2D" count="1" radix="16"> 5A 0C </i2c_write>/>  
             
    </aardvark>      

    so I manually added the disabling ASSR lines:

    i2cset -y 2 0x2d 0xff 0x07
    i2cset -y 2 0x2d 0x16 0x01
    i2cset -y 2 0x2d 0xff 0x00
    i2cset -y 2 0x2d 0x5a 0x04

    the i2c dump for the bridge shows no errors on f0-f8:


    root@imx8mpsolidrun:~# i2cdump -y 2 0x2d
    No size specified (using byte-data access)
    0 1 2 3 4 5 6 7 8 9 a b c d e f
    00: 36 38 49 53 44 20 20 20 02 00 86 00 00 01 00 00
    10: 26 00 6c 00 00 00 00 00 00 00 00 00 00 00 00 00
    20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    30: 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 00
    40: 01 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00
    50: 00 00 00 00 00 00 20 00 40 e4 05 00 10 00 b0 00
    60: a0 60 a4 00 01 00 00 00 00 00 00 00 00 00 00 00
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    80: 00 00 00 00 00 00 00 00 00 1f 7c f0 c1 07 1f 7c
    90: f0 c1 07 04 80 00 00 04 01 00 00 00 00 00 00 00
    a0: 01 ff ff 00 00 00 00 00 00 00 00 00 00 00 00 00
    b0: 04 78 ac ac 08 6c 9c 9c 0c 5c 5c 5c 0c 0c 0c 0c
    c0: 3f 3f 0f 00 00 00 00 00 00 00 00 00 00 00 00 00
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    f0: 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00

    Thanks.

  • I managed to get the no/ASSR script calculated in the .xlsm but still got the same node error.

    the new i2cdump:

    root@imx8mpsolidrun:~# i2cdump -y -a 2 0x2d
    No size specified (using byte-data access)
    0 1 2 3 4 5 6 7 8 9 a b c d e f 0123456789abcdef
    00: 36 38 49 53 44 20 20 20 02 00 06 00 00 00 00 00 68ISD ?.?.....
    10: 3e 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >...............
    20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    40: 01 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 ?...?...........
    50: 00 00 00 00 00 00 20 00 40 e4 05 00 10 00 b0 00 ...... .@??.?.?.
    60: a0 60 a4 00 00 00 00 00 00 00 00 00 00 00 00 00 ?`?.............
    70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    80: 00 00 00 00 00 00 00 00 00 1f 7c f0 c1 07 1f 7c .........?|????|
    90: f0 c1 07 04 00 00 00 04 01 00 00 00 00 00 00 00 ????...??.......
    a0: 01 ff ff 00 00 00 00 00 00 00 00 00 00 00 00 00 ?...............
    b0: 04 78 ac ac 08 6c 9c 9c 0c 5c 5c 5c 0c 0c 0c 0c ?x???l???\\\????
    c0: 3f 3f 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 ???.............
    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
    f0: 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 .....?..........

    thanks.

  • Hello, Shlomi,

    From reading the error it seems like the kernel cannot find the display panel node. 

    From reading the register 0xF5 it looks like the device recognizes a HPD insertion from the display.

    Just to be sure have you tried following the EVM's user guide Section 3 already?

    Thanks,

    Zach

  • Hi Zach,

    yes, I went over the EVM user guide.

    I'm able to get the color bar on the DP using the i2c.

    in the dts - what compatibility should be in the panel node?

    I've set it to "panel-dpi" which looks like it should fit generic panels in the panel-simple driver but still no luck.

    the display is a DELL P272OD.

    thanks.

  • Hello, Shlomi,

    If you have the color bar working, I would recommend checking with the MIPI DSI source vendor on why you are getting a panel node to target. Additionally, you could check to see MIPI DSI signals coming through on a scope into the DSI86 device after you understand from the MIPI DSI source vendor what could be causing the panel node identification issue.

    Thanks,

    Zach

  • Hi,

    the bridge driver finishes loading successfully now without the panel node error :)

    the display still doesn't show any image though (like it would on HDMI directly on our EVB), I'm not sure if the display timings are configured correctly.

    does the panel info have to be via registers in the dts or does programming them via an i2c script and then loading the driver module good enough?

    does the ASSR has to be disabled for the DP monitor? are there any exceptional DP monitors that may not work as expected with this bridge?

    thanks,

  • Hi, Shlomi,

    The default for the DSI86 is ASSR enabled operating mode so some possible problems are that either your display is not enabled for ASSR or that your display does not support ASSR. These two problems can be resolved by following the link below:

    https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945403/faq-sn65dsi86-sn65dsi86-black-screen-debugging-guide

    Thanks,

    Zach