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Original question:

DS125DF410: Fixed divider setting for the CDR

DS125DF410: Any upper limit to the EOM_TIMER_THRx setting?

child sun
Prodigy 190 points
Part Number: DS125DF410

Hi TI Team,

We have been playing with the EOM_TIMER_THRx registers by changing the threshold value from the default 0x30 to other higher values. The datasheet said it could go all the way to 0xff. However, we found that the maximum value has to be lowered in order to read out the EOM error counts properly. Are there any other considerations to increase the threshold value?

Case 1: 6Gbps, Reg 0x2a = 0x30 (default value)

Case 2: 6Gbps, Reg 0x2a = 0xff

When we set 0x2a to 0xff, the error count readout is wrong (with channel 0). Is that what we should expect? Why?

Thanks.

Child

  • 0
    TI__Mastermind 21685 points

    Hi Child,

    I haven't seen an issue like this before. I'm especially surprised that the EOM only caused issues on one of the 4 channels. I'm going to try replicating your issue at a lab bench and I'll get back to you with what I find.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    Prodigy 190 points

    Lucas,

    Yes, it's kind of weird. I also noticed that the issue can be bit rate dependent as well. For example, through trial and error, it's ok to set reg 0x2a to 0xcf at 6Gbps. However, the same threshold value will create issue to the data rate of 1.25Gbps.

    Child

  • 0 in reply to child sun
    TI__Mastermind 21685 points

    Hi Child,

    I'm still working on trying to replicate your results. In the mean time, can you provide some more details about your setup? What type of data is being sent to the retimer? Can you provide a full register dump in a case where EOM is working and a case where EOM isn't working?

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    Prodigy 190 points

    Lucas,

    I was sending in PRBS-9 data to the receiving EVM. I used another EVM to generate the PRBS data (in free-running VCO mode).

    Here are our initialization sequences for reference:

    # TX initialization
    wrm(0xff, 0x0c, 0xff) # write to all ch
    wrm(0x30, 0x00, 0x08) # disable prbs_en_dig_clk
    wrm(0x00, 0x08, 0x08) # rest CORE state machine
    wrm(0x00, 0x04, 0x04) # rest registers
    wrm(0x00, 0x03, 0x03) # rest reference clock domain and VCO div domain
    wrm(0x09, 0xfc, 0xff) # override a few controls
    wrm(0x14, 0x80, 0xc0) # force signal detect
    wrm(0x1b, 0x00, 0x03) # disable charge pump
    wrm(0x18, 0x10, 0x70) # set VCO divider
    wrm(0x08, 0x02, 0x1f) # VCO cap count (needs to be adjusted to get the right rate 6Gbps for each channel)
    wrm(0x1f, 0x08, 0x1f) # VCO LPF DAC (needs to be adjusted to get the right rate 6Gbps for each channel)
    wrm(0x1e, 0x80, 0xe0) # select PRBS generator
    wrm(0x1e, 0x10, 0x10) # enable PRBS generator
    wrm(0x30, 0x00, 0x03) # PRBS-9
    wrm(0x0d, 0x20, 0x20) # enable PRBS pattern shift
    wrm(0x30, 0x08, 0x08) # enable prbs_en_dig_clk

    # RX initialization
    wrm(0xff, 0x0c, 0xff) # write to all ch
    wrm(0x00, 0x04, 0x04) # Reset channel registers, self-clearing
    wrm(0x2f, 0x60, 0xf0) # all rates (div 1~8)
    wrm(0x31, 0x00, 0x60) # Set Adapt Mode 0 (no adaptation)
    wrm(0x03, eq, 0xff) # EQ=0x00 (or select the right value depending on the channel loss)
    wrm(0x3A, 0x00, 0xff) # Same as Reg_0x03 (Fixed EQ Boost setting)
    wrm(0x40, 0x00, 0xff) # Same as Reg_0x03 (CTLE adaptation Index#0 register value)
    wrm(0x1e, 0x08, 0x08) # Power down DFE
    wrm(0x2d, 0x08, 0x08) # Enable overriding the EQ setting from 0x03 register setting
    wrm(0x2d, 0x02, 0x07) # Configure VOD, 800 mV
    wrm(0x15, 0x00, 0x47) # Configure the DEM, 0 db
    wrm(0x2a, 0x30, 0xff) # Eye error accumulation time setting (default: 0x30)
    # set expected freq to lock to (here tx_freq = 6Gbps)
    ppm = int(tx_freq * 1280)
    ppm_lsb = ppm & 0xff
    ppm_msb = ppm >> 8 | 0x80
    wrm(0x60, ppm_lsb, 0xff)
    wrm(0x62, ppm_lsb, 0xff)
    wrm(0x61, ppm_msb, 0xff)
    wrm(0x63, ppm_msb, 0xff)
    wrm(0x64, 0xff, 0xff)
    wrm(0x18, 0x10, 0x70) # set vco divide factor
    wrm(0x0a, 0x0c, 0x0c) # Assert CDR reset
    wrm(0x0a, 0x00, 0x0c) # Release CDR reset
    wrm(0x2f, 0x00, 0x04) # disable PPM check
    wrm(0x0c, 0x08, 0x08) # enable sbt check
    wrm(0x2f, 0x60, 0xf0)

    ** where wrm is a register write function: wrm(reg address, value, mask)

    The only difference between the working case and non-working case is the setting of the reg 0x2a.

    Thanks.

    Child

  • 0 in reply to child sun
    TI__Mastermind 21685 points

    Hi Child,

    Thanks for sharing, could you also share a full register dump of all register values at the time when eye scan is taken? Could you share both in a situation where EOM is working and when EOM is not working? It would be helpful for me to see status register values to better understand what's happening with the retimer.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    Prodigy 190 points

    Hi Lucas,

    Sorry for the delay in responding. Here are the register dumps.

    When reg 0x2a = 0x30:

    Ch0 page registers
    0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf
    ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
    0x0: 0x0 0x0 0x9c 0x0 0x0 0x0 0x0 0x0 0x0 0x4 0x10 0xf 0x8 0x0 0x93 0x69
    0x1: 0x3a 0xa0 0xa0 0x30 0x0 0x10 0x7a 0x36 0x10 0x23 0x0 0x3 0x24 0x0 0xe9 0x55
    0x2: 0x0 0x0 0x0 0x40 0x0 0xb 0xf0 0x33 0x7b 0x40 0x30 0x0 0x72 0x8a 0x0 0x62
    0x3: 0x0 0x0 0x11 0x88 0xbf 0x1f 0x31 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80 0x0
    0x4: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0x5: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0x6: 0x0 0xbc 0x0 0xbc 0xff 0x0 0x0 0x20 0x0 0xa 0x44 0x0 0x0 0x0 0x0 0x0
    0x7: 0x3 0x20 0x0 0x0 0x0 0x0 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0x8: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0x9: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xa: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xb: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xc: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xd: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xe: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xf: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5

    Ch1 page registers
    0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf
    ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
    0x0: 0x0 0x0 0xdc 0x0 0x0 0x0 0x0 0x0 0x0 0x4 0x10 0xf 0x8 0x0 0x93 0x69
    0x1: 0x3a 0xa0 0xa0 0x30 0x0 0x10 0x7a 0x36 0x10 0x23 0x0 0x3 0x24 0x0 0xe9 0x55
    0x2: 0x0 0x0 0x0 0x40 0x0 0xb 0xf7 0x35 0x75 0x40 0x30 0x0 0x72 0x8a 0x0 0x62
    0x3: 0x0 0x0 0x11 0x88 0xbf 0x1f 0x31 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80 0x0
    0x4: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0x5: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0x6: 0x0 0xbc 0x0 0xbc 0xff 0x0 0x0 0x20 0x0 0xa 0x44 0x0 0x0 0x0 0x0 0x0
    0x7: 0x3 0x20 0x0 0x0 0x0 0x0 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0x8: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0x9: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xa: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xb: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xc: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xd: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xe: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xf: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5

    Ch2 page registers
    0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf
    ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
    0x0: 0x0 0x0 0xdc 0x0 0x0 0x0 0x0 0x0 0x0 0x4 0x10 0xf 0x8 0x0 0x93 0x69
    0x1: 0x3a 0xa0 0xa0 0x30 0x0 0x10 0x7a 0x36 0x10 0x23 0x0 0x3 0x24 0x0 0xe9 0x55
    0x2: 0x0 0x0 0x0 0x40 0x3 0xc 0x12 0x34 0x87 0x40 0x30 0x0 0x72 0x8a 0x0 0x62
    0x3: 0x0 0x0 0x11 0x88 0xbf 0x1f 0x31 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80 0x0
    0x4: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0x5: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0x6: 0x0 0xbc 0x0 0xbc 0xff 0x0 0x0 0x20 0x0 0xa 0x44 0x0 0x0 0x0 0x0 0x0
    0x7: 0x3 0x20 0x0 0x0 0x0 0x0 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0x8: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0x9: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xa: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xb: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xc: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xd: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xe: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xf: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5

    Ch3 page registers
    0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf
    ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
    0x0: 0x0 0x0 0xdc 0x0 0x0 0x0 0x0 0x0 0x0 0x4 0x10 0xf 0x8 0x0 0x93 0x69
    0x1: 0x3a 0xa0 0xa0 0x30 0x0 0x10 0x7a 0x36 0x10 0x23 0x0 0x3 0x24 0x0 0xe9 0x55
    0x2: 0x0 0x0 0x0 0x40 0x0 0xc 0x3 0x33 0x7e 0x40 0x30 0x0 0x72 0x8a 0x0 0x62
    0x3: 0x0 0x0 0x11 0x88 0xbf 0x1f 0x31 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80 0x0
    0x4: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0x5: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0x6: 0x0 0xbc 0x0 0xbc 0xff 0x0 0x0 0x20 0x0 0xa 0x44 0x0 0x0 0x0 0x0 0x0
    0x7: 0x3 0x20 0x0 0x0 0x0 0x0 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0x8: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0x9: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xa: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xb: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xc: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xd: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xe: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xf: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5

    Ctrl page registers
    0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf
    ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
    0x0: 0x0 0xd1 0x0 0x0 0x1 0x0 0x0 0x4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0x1: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0x2: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0x3: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0x4: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0x5: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0x6: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0x7: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0x8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0x9: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0xa: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0xb: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0xc: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0xd: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0xe: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0xf: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

    When reg 0x2a = 0xff:

    Ch0 page registers
    0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf
    ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
    0x0: 0x0 0x10 0xdc 0x0 0x0 0x0 0x0 0x0 0x0 0x4 0x10 0xf 0x8 0x0 0x93 0x69
    0x1: 0x3a 0xa0 0xa0 0x30 0x0 0x10 0x7a 0x36 0x10 0x23 0x0 0x3 0x24 0x0 0xe9 0x55
    0x2: 0x0 0x0 0x0 0x40 0x0 0x38 0x35 0x33 0x78 0x40 0xff 0x0 0x72 0x8a 0x0 0x62
    0x3: 0x0 0x0 0x11 0x88 0xbf 0x1f 0x31 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80 0x0
    0x4: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0x5: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0x6: 0x0 0xbc 0x0 0xbc 0xff 0x0 0x0 0x20 0x0 0xa 0x44 0x0 0x0 0x0 0x0 0x0
    0x7: 0x3 0x20 0x0 0x0 0x0 0x0 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0x8: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0x9: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xa: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xb: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xc: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xd: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xe: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xf: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5

    Ch1 page registers
    0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf
    ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
    0x0: 0x0 0x0 0xdc 0x0 0x0 0x0 0x0 0x0 0x0 0x4 0x10 0xf 0x8 0x0 0x93 0x69
    0x1: 0x3a 0xa0 0xa0 0x30 0x0 0x10 0x7a 0x36 0x10 0x23 0x0 0x3 0x24 0x0 0xe9 0x55
    0x2: 0x0 0x0 0x0 0x40 0x0 0x38 0x59 0x33 0x75 0x40 0xff 0x0 0x72 0x8a 0x0 0x62
    0x3: 0x0 0x0 0x11 0x88 0xbf 0x1f 0x31 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80 0x0
    0x4: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0x5: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0x6: 0x0 0xbc 0x0 0xbc 0xff 0x0 0x0 0x20 0x0 0xa 0x44 0x0 0x0 0x0 0x0 0x0
    0x7: 0x3 0x20 0x0 0x0 0x0 0x0 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0x8: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0x9: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xa: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xb: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xc: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xd: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xe: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xf: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5

    Ch2 page registers
    0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf
    ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
    0x0: 0x0 0x10 0xdc 0x0 0x0 0x0 0x0 0x0 0x0 0x4 0x10 0xf 0x8 0x0 0x93 0x69
    0x1: 0x3a 0xa0 0xa0 0x30 0x0 0x10 0x7a 0x36 0x10 0x23 0x0 0x3 0x24 0x0 0xe9 0x55
    0x2: 0x0 0x0 0x0 0x40 0x0 0x3d 0x80 0x33 0x84 0x40 0xff 0x0 0x72 0x8a 0x0 0x62
    0x3: 0x0 0x0 0x11 0x88 0xbf 0x1f 0x31 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80 0x0
    0x4: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0x5: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0x6: 0x0 0xbc 0x0 0xbc 0xff 0x0 0x0 0x20 0x0 0xa 0x44 0x0 0x0 0x0 0x0 0x0
    0x7: 0x3 0x20 0x0 0x0 0x0 0x0 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0x8: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0x9: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xa: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xb: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xc: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xd: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xe: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xf: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5

    Ch3 page registers
    0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf
    ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
    0x0: 0x0 0x0 0x9c 0x0 0x0 0x0 0x0 0x0 0x0 0x4 0x10 0xf 0x8 0x0 0x93 0x69
    0x1: 0x3a 0xa0 0xa0 0x30 0x0 0x10 0x7a 0x36 0x10 0x23 0x0 0x3 0x24 0x0 0xe9 0x55
    0x2: 0x0 0x0 0x0 0x40 0x3 0x4 0x1f 0x32 0x78 0x40 0xff 0x0 0x72 0x8a 0x0 0x62
    0x3: 0x0 0x0 0x11 0x88 0xbf 0x1f 0x31 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x80 0x0
    0x4: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0x5: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0x6: 0x0 0xbc 0x0 0xbc 0xff 0x0 0x0 0x20 0x0 0xa 0x44 0x0 0x0 0x0 0x0 0x0
    0x7: 0x3 0x20 0x0 0x0 0x0 0x0 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0x8: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0x9: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xa: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xb: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xc: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xd: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5
    0xe: 0x0 0x1 0x4 0x10 0x40 0x8 0x2 0x80 0x3 0xc 0x30 0x41 0x50 0xc0 0x60 0x90
    0xf: 0x88 0x82 0xa0 0x46 0x52 0x8c 0xb0 0xc8 0x57 0x5d 0x69 0x75 0xd5 0x99 0x96 0xa5

    Ctrl page registers
    0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf
    ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
    0x0: 0x0 0xd1 0x0 0x0 0x1 0x0 0x0 0x4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0x1: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0x2: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0x3: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0x4: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0x5: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0x6: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0x7: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0x8: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0x9: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0xa: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0xb: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0xc: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0xd: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0xe: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
    0xf: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

  • 0 in reply to child sun
    TI__Mastermind 21685 points

    Hi Child,

    Thanks for providing register dumps, I don't immediately see anything that could be causing the issue. Have you performed a BER check on the system and is it running error free? Is there any difference in the inputs to channel 0 versus the other channels?

    Also, can you try setting register 0x2f = 0xa2 to force a divider ratio of 2? One theory I had is that the retimer is potentially locking to the incorrect subrate.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    Prodigy 190 points

    Lucas,

    We did check the divider ratios on each of the channels. They all locked correctly. Here is the status:

    ** Status: Ch 0
    CDR_LOCK_LOSS_INT: 0
    SIG_DET_LOSS_INT: 0
    PPM Count met: 1
    Auto Adapt Complete: 0
    Fail Lock Check: 0
    Lock: 1
    CDR Lock: 1
    Single Bit Limit Reached: 1
    Comp LPF High: 0
    Comp LPF Low: 0
    EOM Counter: 16561
    HEO (UI): 0.75
    VEO (mV): 300.00
    EOM Voltage Range Setting: +/-300mV
    Divider Ratio: 2

    ** Status: Ch 1
    CDR_LOCK_LOSS_INT: 1
    SIG_DET_LOSS_INT: 0
    PPM Count met: 1
    Auto Adapt Complete: 1
    Fail Lock Check: 0
    Lock: 1
    CDR Lock: 1
    Single Bit Limit Reached: 1
    Comp LPF High: 0
    Comp LPF Low: 0
    EOM Counter: 14188
    HEO (UI): 0.73
    VEO (mV): 290.62
    EOM Voltage Range Setting: +/-300mV
    Divider Ratio: 2


    ** Status: Ch 2
    CDR_LOCK_LOSS_INT: 0
    SIG_DET_LOSS_INT: 0
    PPM Count met: 1
    Auto Adapt Complete: 1
    Fail Lock Check: 0
    Lock: 1
    CDR Lock: 1
    Single Bit Limit Reached: 1
    Comp LPF High: 0
    Comp LPF Low: 0
    EOM Counter: 15903
    HEO (UI): 0.77
    VEO (mV): 328.12
    EOM Voltage Range Setting: +/-300mV
    Divider Ratio: 2

    ** Status: Ch 3
    CDR_LOCK_LOSS_INT: 0
    SIG_DET_LOSS_INT: 0
    PPM Count met: 1
    Auto Adapt Complete: 0
    Fail Lock Check: 0
    Lock: 1
    CDR Lock: 1
    Single Bit Limit Reached: 1
    Comp LPF High: 0
    Comp LPF Low: 0
    EOM Counter: 8124
    HEO (UI): 0.75
    VEO (mV): 459.38
    EOM Voltage Range Setting: +/-300mV
    Divider Ratio: 2

    Did you manage to reproduce the issues in your lab?

    Thanks.

    Child

  • 0 in reply to child sun
    TI__Mastermind 21685 points

    Hi Child,

    I tried to reproduce the issue in lab but I did not see the same result as you, the EOM performed as expected. With these statuses you just sent, was the eye scan wrong on channels 0 and 3? I noticed both of these channels have not completed auto adapt, so I'm wondering if this may be causing the EOM issues.

    Best,

    Lucas