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DS90UB933-Q1: Regarding I2C bus contention.

Masanori Okano
Prodigy 230 points
Part Number: DS90UB933-Q1

Hi Team,

I have a SoC connected to the serializer as a host.
I thought that if a remote access comes from the deserializer while the host is setting registers in the serializer, there will be an I2C bus contention.

I drew a simple image diagram, please refer to it.

20230127.pdf

Question 1.
Is this a possible problem?

Question 2
If it can happen, how to avoid it?
Is it necessary to design the timing so that the access cycle and access timing do not match?

Best Regards,

  • +1
    TI__Genius 11315 points

    Hi Masanori, 

    Yes, an I2C contention is possible in this scenario. It is ultimately up to the user to implement a mechanism to handle the multi-master scenarios. If you are designing both sides of the link, one suggestion is utilizing spare registers to coordinate transactions on the I2C bus. There are mailbox registers in the 954 specifically for this purpose (0x78-0x79). Two I2C masters on opposite ends of the link can avoid contention by passing messages through these spare registers. For example, the mailbox can be set to a value when the SOC is using the bus and unset once the SOC releases ownership of the bus. Please see attached material for a more detailed example of the mailbox mechanism.

    Regards,

    Cindy

    4452.Mailbox_Mechanism.pdf

  • 0 in reply to Cindy Li
    Prodigy 230 points

    Hi Cindy,

    Thank you for your response.
    I understand and will close it.
    We will inquire again if any questions arise when we implement it.

    Regards,

    Masanori