Hi team,
would you please help me to review the schematic(Page.2) and layout(.PCB file) of DS90UB926Q-Q1?
the case info below:
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Project name: |
EL-321W-GL0J |
|
End equipment: |
Geely |
|
End Customer/region |
CN |
|
PM: |
古亞力 |
|
EE RD: |
葉孟和 |
|
Platform: |
MCU |
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Status : |
P1樣品 |
|
Layout time: |
12/27 ~ 1/17 P1 3/28 ~ 4/7 P2 |
|
MP date: |
2023/10E |
|
Qty per year: |
4_tear |
TI 3P321WGA043-0A.PCB3P321WGA043-0A SCH(0202).pdf
BR,
Jimmy
Hi Jimmy,
Here are my schematic notes: 3P321WGA043-0A SCH(0202)_Reviewed.pdf
As for the layout:
If possible, reduce the AC Coupling caps down from size 0603 to size 0402 as they should have less impact on high speed SI.
Creating an anti-pad on the layer under the device pins and AC caps should help reduce any parasitic capacitance and maintain differential impedance.
Ensure the trace length of the FPD P/N lanes are matching within the TI recommended +/- 5mils
An anti-pad under diodes and CMCs should also help with parasitic capacitance.
Ensure via simulation or with the connector vendor that the thru-hole vias maintain a 100Ohm controlled impedance.
Finally, make sure to follow the datasheet to ensure proper thermal pad layout is being followed.
Thanks,
Ryan
