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DS90UB960-Q1: REFCLK register value is different from the measured frequency by oscilloscope

roman ivnitzki
Prodigy 40 points

Part Number: DS90UB960-Q1
Other Parts Discussed in Thread: ALP, USB2ANY

Hello,

Our team is developing a board that uses two DS90UB960's.   We had problems with instability and failed locking\pass so we connected USB2ANY and monitored the status through the ALP.
We have noticed that the deserializer measures the REFCLK as 28Mhz even though we are certainly feeding it with a 25Mhz clock.  What can be the reason?

This is the 25Mhz clock we are feeding:


We tried to "fool" the deserializer  by providing it with a 22Mhz clock and it actually worked. The reported REFCLK became 25Mhz and Lock\Pass became stable without errors. (bottom picture)
Also attached register dumps from the serializer\deserializer while feeding the deserializer with 22Mhz.



953_registers.nrd:

[REGISTERS]
Device = ALP Nano 1 - DS90UB953, Connector 1
Comments = "953_registers"
Date = 02/12/2023
Time = 22:24:34
Reg = 0,0x0000,0x30
Reg = 0,0x0001,0x00
Reg = 0,0x0002,0x33
Reg = 0,0x0003,0x48
Reg = 0,0x0004,0x00
Reg = 0,0x0005,0x03
Reg = 0,0x0006,0x41
Reg = 0,0x0007,0x28
Reg = 0,0x0008,0xFE
Reg = 0,0x0009,0x1E
Reg = 0,0x000A,0x10
Reg = 0,0x000B,0x7F
Reg = 0,0x000C,0x7F
Reg = 0,0x000D,0xF0
Reg = 0,0x000E,0x0F
Reg = 0,0x0010,0x00
Reg = 0,0x0011,0x00
Reg = 0,0x0013,0x00
Reg = 0,0x0014,0x00
Reg = 0,0x0015,0x20
Reg = 0,0x0017,0x3C
Reg = 0,0x0018,0x80
Reg = 0,0x0019,0x62
Reg = 0,0x001A,0x62
Reg = 0,0x001B,0x62
Reg = 0,0x001C,0x00
Reg = 0,0x001D,0x00
Reg = 0,0x001E,0x00
Reg = 0,0x0020,0x00
Reg = 0,0x0021,0x00
Reg = 0,0x0022,0x00
Reg = 0,0x0023,0x00
Reg = 0,0x0024,0x00
Reg = 0,0x0031,0x20
Reg = 0,0x0032,0x09
Reg = 0,0x0033,0x04
Reg = 0,0x0035,0x11
Reg = 0,0x0037,0x7A
Reg = 0,0x0039,0x00
Reg = 0,0x003A,0x00
Reg = 0,0x003B,0x00
Reg = 0,0x003C,0x00
Reg = 0,0x003D,0x00
Reg = 0,0x003E,0x00
Reg = 0,0x003F,0x00
Reg = 0,0x0040,0x00
Reg = 0,0x0041,0x00
Reg = 0,0x0042,0x00
Reg = 0,0x0043,0x00
Reg = 0,0x0044,0x00
Reg = 0,0x0045,0x00
Reg = 0,0x0046,0x00
Reg = 0,0x0047,0x00
Reg = 0,0x0048,0x00
Reg = 0,0x0049,0x00
Reg = 0,0x0050,0x20
Reg = 0,0x0051,0xC0
Reg = 0,0x0052,0x45
Reg = 0,0x0053,0x06
Reg = 0,0x0054,0x00
Reg = 0,0x0055,0x00
Reg = 0,0x0056,0x00
Reg = 0,0x0057,0x00
Reg = 0,0x0058,0x07
Reg = 0,0x0059,0x07
Reg = 0,0x005A,0x07
Reg = 0,0x005C,0x00
Reg = 0,0x005D,0x00
Reg = 0,0x005E,0x00
Reg = 0,0x005F,0x00
Reg = 0,0x0060,0x00
Reg = 0,0x0061,0x00
Reg = 0,0x0062,0x00
Reg = 0,0x0063,0x00
Reg = 0,0x0064,0x00
Reg = 0,0x00B0,0x04
Reg = 0,0x00B1,0x4A
Reg = 0,0x00B2,0x3F
Reg = 0,0x00F0,0x5F
Reg = 0,0x00F1,0x55
Reg = 0,0x00F2,0x42
Reg = 0,0x00F3,0x39
Reg = 0,0x00F4,0x35
Reg = 0,0x00F5,0x33


960_registers.nrd:
[REGISTERS]
Device = ALP Nano 1 - DS90UB960, Connector 1
Comments = "960"
Date = 02/12/2023
Time = 22:24:10
Reg = 0,0x0000,0x7A
Reg = 0,0x0001,0x00
Reg = 0,0x0002,0x1E
Reg = 0,0x0003,0x40
Reg = 0,0x0004,0xD0
Reg = 0,0x0005,0x01
Reg = 0,0x0006,0x00
Reg = 0,0x0007,0xFE
Reg = 0,0x0008,0x1C
Reg = 0,0x0009,0x10
Reg = 0,0x000A,0x7A
Reg = 0,0x000B,0x7A
Reg = 0,0x000C,0x0F
Reg = 0,0x000D,0x09
Reg = 0,0x000E,0x00
Reg = 0,0x000F,0xFF
Reg = 0,0x0010,0x00
Reg = 0,0x0011,0x00
Reg = 0,0x0012,0x00
Reg = 0,0x0013,0x00
Reg = 0,0x0014,0x00
Reg = 0,0x0015,0x00
Reg = 0,0x0016,0x00
Reg = 0,0x0017,0x00
Reg = 0,0x0018,0x00
Reg = 0,0x0019,0x00
Reg = 0,0x001A,0x00
Reg = 0,0x001B,0x00
Reg = 0,0x001C,0x00
Reg = 0,0x001D,0x00
Reg = 0,0x001E,0x04
Reg = 0,0x001F,0x02
Reg = 0,0x0020,0xF0
Reg = 0,0x0021,0x03
Reg = 0,0x0022,0x00
Reg = 0,0x0023,0x00
Reg = 0,0x0024,0x00
Reg = 0,0x0025,0x00
Reg = 0,0x0026,0x00
Reg = 0,0x0027,0x00
Reg = 0,0x0028,0x00
Reg = 0,0x0029,0x00
Reg = 0,0x002A,0x00
Reg = 0,0x002B,0x00
Reg = 0,0x002C,0x00
Reg = 0,0x002D,0x00
Reg = 0,0x002E,0x00
Reg = 0,0x002F,0x00
Reg = 0,0x0030,0x00
Reg = 0,0x0031,0x00
Reg = 0,0x0032,0x00
Reg = 0,0x0033,0x00
Reg = 0,0x0034,0x00
Reg = 0,0x0035,0x00
Reg = 0,0x0036,0x00
Reg = 0,0x0037,0x00
Reg = 0,0x0038,0x00
Reg = 0,0x0039,0x00
Reg = 0,0x003A,0x00
Reg = 0,0x0040,0x00
Reg = 0,0x0041,0xA9
Reg = 0,0x0042,0x71
Reg = 0,0x0043,0x01
Reg = 0,0x0044,0x00
Reg = 0,0x0045,0x00
Reg = 0,0x0046,0x20
Reg = 0,0x0047,0x00
Reg = 0,0x004C,0x00
Reg = 0,0x004D,0x03
Reg = 0,0x004E,0x0C
Reg = 0,0x004F,0x64
Reg = 0,0x0050,0x00
Reg = 0,0x0051,0x00
Reg = 0,0x0052,0x00
Reg = 0,0x0053,0x03
Reg = 0,0x0054,0x00
Reg = 0,0x0055,0x00
Reg = 0,0x0056,0xA1
Reg = 0,0x0057,0x00
Reg = 0,0x0058,0x5E
Reg = 0,0x0059,0x00
Reg = 0,0x005A,0x00
Reg = 0,0x005B,0x30
Reg = 0,0x005C,0x18
Reg = 0,0x005D,0x00
Reg = 0,0x005E,0x00
Reg = 0,0x005F,0x00
Reg = 0,0x0060,0x00
Reg = 0,0x0061,0x00
Reg = 0,0x0062,0x00
Reg = 0,0x0063,0x00
Reg = 0,0x0064,0x00
Reg = 0,0x0065,0x00
Reg = 0,0x0066,0x00
Reg = 0,0x0067,0x00
Reg = 0,0x0068,0x00
Reg = 0,0x0069,0x00
Reg = 0,0x006A,0x00
Reg = 0,0x006B,0x00
Reg = 0,0x006C,0x00
Reg = 0,0x006D,0x7C
Reg = 0,0x006E,0x88
Reg = 0,0x006F,0x88
Reg = 0,0x0070,0x2B
Reg = 0,0x0071,0x2C
Reg = 0,0x0072,0xE4
Reg = 0,0x0073,0x00
Reg = 0,0x0074,0x00
Reg = 0,0x0075,0x00
Reg = 0,0x0076,0x00
Reg = 0,0x0077,0xC5
Reg = 0,0x0078,0x00
Reg = 0,0x0079,0x01
Reg = 0,0x007A,0x0F
Reg = 0,0x007B,0xFF
Reg = 0,0x007C,0x20
Reg = 0,0x007D,0x00
Reg = 0,0x007E,0x00
Reg = 0,0x007F,0x00
Reg = 0,0x0090,0x00
Reg = 0,0x0091,0x00
Reg = 0,0x0092,0x00
Reg = 0,0x0093,0x00
Reg = 0,0x0094,0x00
Reg = 0,0x0095,0x00
Reg = 0,0x0096,0x00
Reg = 0,0x0097,0x00
Reg = 0,0x0098,0x00
Reg = 0,0x0099,0x00
Reg = 0,0x009A,0x00
Reg = 0,0x009B,0x00
Reg = 0,0x009C,0x00
Reg = 0,0x009D,0x00
Reg = 0,0x009E,0x00
Reg = 0,0x009F,0x00
Reg = 0,0x00A5,0x19
Reg = 0,0x00B0,0x1C
Reg = 0,0x00B1,0x3A
Reg = 0,0x00B2,0x14
Reg = 0,0x00B3,0x08
Reg = 0,0x00B8,0xFC
Reg = 0,0x00B9,0x33
Reg = 0,0x00BA,0x83
Reg = 0,0x00BB,0x74
Reg = 0,0x00BC,0x80
Reg = 0,0x00BD,0x00
Reg = 0,0x00BE,0x00
Reg = 0,0x00D0,0x00
Reg = 0,0x00D1,0x43
Reg = 0,0x00D2,0x94
Reg = 0,0x00D3,0x0F
Reg = 0,0x00D4,0x60
Reg = 0,0x00D5,0xF2
Reg = 0,0x00D6,0x00
Reg = 0,0x00D7,0x03
Reg = 0,0x00D8,0x00
Reg = 0,0x00D9,0x00
Reg = 0,0x00DA,0x00
Reg = 0,0x00DB,0x00
Reg = 0,0x00DC,0x00
Reg = 0,0x00DD,0x00
Reg = 0,0x00DE,0x00
Reg = 0,0x00DF,0x00
Reg = 0,0x00F0,0x5F
Reg = 0,0x00F1,0x55
Reg = 0,0x00F2,0x42
Reg = 0,0x00F3,0x39
Reg = 0,0x00F4,0x36
Reg = 0,0x00F5,0x30
Reg = 0,0x00F8,0x00
Reg = 0,0x00F9,0x00
Reg = 0,0x00FA,0x00
Reg = 0,0x00FB,0x00

Edit:

Ive found simmilar threads here but none of them gave a solution/explanation for the root cause. We have measured our VCCIO (1.8) and 3.3/2.5.  All voltages are stable.

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/904763/ds90ub960-q1evm-ds90ub960-q1evm-refclk-pin-input-is-25mhz-but-i2c-register-0xa5-of-90960-is-0x1c-28mhz

e2e.ti.com/.../3738416

*files removed*

  • 0
    TI__Genius 16220 points

    Hi Roman,

    Let me look into this. Allow 1-2 working days.

    Glenn 

  • 0 in reply to Glenn Uranga
    Prodigy 40 points

    Hi Glenn. Got it, waiting. Thank you! Our team is prepared to provide any additional info/tests necessary

  • 0 in reply to roman ivnitzki
    TI__Genius 16220 points

    Thanks Roman,

    Let me review before requesting more information.

    Glenn 

  • 0 in reply to Glenn Uranga
    Prodigy 40 points

    Hi Glenn, do you have any insights?

  • 0 in reply to roman ivnitzki
    TI__Genius 16220 points

    Hi Roman,

    Here is what I am thinking:

    1. Repeat the test with just one active Rx port, and disable the other unused ports.
      1. If that does not help, complete a digital reset (reg 0x01[0]) and check if reset recovers the issue.
      2. If that does not solve the issue, try to test using another Oscillator (different manufacturer)
      3. If that does not help, try another DES board

    Glenn 

  • 0 in reply to Glenn Uranga
    Prodigy 40 points

    Hi,

    We have tried the suggested tests but the results stay the same. The deserializer always reports 28Mhz on REFCLK when providing 25MHz from various sources.  Providing lower clocks (twards 22Mhz) seems to make the connection more stable on our tested devices.

    Is there a variance in the way the deserializers are produces or do they have some configurations that are not accesible from the registers/permanent after power cycle?

    As I've mentioned in the post there are multiple posts here mentioning  28Mhz  on REFCLK when providing 25Mhz. Right now our focus is investigating the reason behind the diffrance although we are not entirely sure its an issue.

    I've read on the datasheet that the REFCLK is measured by the internal oscillator that can have +/-10% error.  If that is the case we should be seeing maximum 27Mhz. 

    Are there other resources about the internal oscilllator? 

    Thank you,

    Roman

  • 0 in reply to roman ivnitzki
    TI__Guru** 116930 points

    Hello Roman,

    Seeing 28MHz is not an issue. This is measurement variations due to tolerances of the Internal Oscillator.

    Have you tried the steps recommended by Glenn to see if any helps to resolve the instability issue?

    Additionally, can you measure the power-up sequence of the devices, including REFCLK on the plot?

  • 0 in reply to Hamzeh Jaradat
    Prodigy 40 points

    Hello, 

    Yes we have tried the steps recommended by Glennn but that did not resolved the stability issue.

    After alot of trial and error we have decided to try to use non-sync with internal osc by configuring the serializer(953) mode voltage. This reduced the fpd link speed to 50Mhz (osccal=0). With that setup the link looks stable on all ports and cable lengths. We have tried to configure pattern generation in the 953 via the launchpad and it also worked. Due to the use of non-sync internal connection we no longer have clock output for our camera sensor so we willl be able to test actual video link only next week after we make the adjustments to the hardware and software.

    This experiment probably points to layout design issues (lower frequency, less problems). We have a short schedual so we cannot halt the development and produce a fixed hardware board. We also do not know what is the problem in our layout (if its there).  Is this the place to ask for someone to look at it? Specifically the connection between the SMA and descirializer ports.

    Will update on results next week.

    Thank you,

    Roman.

  • 0 in reply to roman ivnitzki
    TI__Guru** 116930 points

    Hello Roman,

    Thanks for the update. 

    I agree that this is a layout/design issue which is working fine up to certain frequencies. If you use the 22MHz REFCLK, your forward channel datarate will run at 22x160 = 3520 Mbps which has a frequency of 1760MHz, where using 25MHz REFCLK means your datarate is 4Gbps and your forward channel frequency is 2HGz.

    That being said, it looks like your layout or PoC filter has some issue at frequencies above 1760MHz. If you want, we can review your schematic and layout if you provide those.

  • 0 in reply to Hamzeh Jaradat
    Prodigy 40 points

    It will be very helpfull.  The schematic and layout is attached at the end of the post itself (at the bottom), can you see them?

    Side note:

    The manufacturer has confirmed the inputs are 50ohm impedance and the layout designer says he did everything "by the book".

  • 0 in reply to roman ivnitzki
    TI__Guru** 116930 points

    Hello Roman,

    I can see the files in your first Post. Please be aware that this is a public forum, and anyone can see and download your files. I recommend you delete them from the post, and do not post here any confidential information.

  • +1 in reply to Hamzeh Jaradat
    TI__Guru** 116930 points

    Roman,

    after looking at your layout, I can see some potential issues which can cause such behavior. See the attached review file.

    DS90UB960 Layout Review.pptx