SN65DP159: No response of SN65DP159 IIC interface (SCL/SDA_CTL)

Jason

Any chance you can send a board to me for testing in my lab?

Thanks

David

Hi, David:

TI have support or lab in China?

Thanks in advance！

Best regards

Jason

Hi, David:

It seems that below thread have the same IIC_CTL problem with me. So, Do you remember how the poster resolve this problem?

e2e.ti.com/.../sn65dp159-not-giving-ack-not-detected-in-i2c-probe

Thanks in advance!

Best regards!

Jason

Jason

He never came back with a response, so I don't know if he is able to solve this problem or not.

For the I2C issue

1. Check power-up sequence, make sure power-up sequence is correct

2. Check DP159 thermal pad connection to the PCB board ground, make sure it is properly connected

3. Check DP159 thermal pad solder coverage, we recommended 73% coverage for this part

4. Can you change A0 and A1 pullup and pulldown to select a different I2C address and see if works?

Thanks

David

Hi, David:

DP159 only require two power rail (3.3V to VCC and 1.1V to VDD) for normal operation. Does the timing spec of td1 must be set and satisfied in the range of 0~200us as below figure shown？

In my design, I use 3.3V to generate 1.1V through one LDO Regulator. But the below test waveform show that 1.1V has reached to its normal voltage ~521us earlier  than 3.3V. The 521us exceed the above 200us range. Will it be the possible root cause for this IIC_CTL problem?

Thanks in advance!

Best regards!

Jason

Jason

If OE is low, Td1 doesn't matter, you just have to meet Td2. OE leave low level 100us after Vcc and Vdd are stable.

Is it possible that you can ship the board to Dallas? 

Thanks

David

Hi， David:

I'm sorry that It is not convenient to ship board to your lab in Dallas. 

As below shown, I pull OE down through 1K resistor on the side of 1.8v range of level shift(TXB0104 from TI too). After the board power on, this make OE keep low level before loading FPGA image. when FPGA finish loading image, OE signal will be set to high level. So, this OE will keep low level for a while after Vcc and Vdd are stable as,  below figure shown. I have two probes, and only test two times for OE and 1.1V VS 3.3v separately.

Up to know, everything is ok for I2C interface of DP159, but it also don't work. So, I only run 1080p video on DP159 which needn't access I2C_CTL.

3.3V(Blue) vs OE (Pink)：

3.3V(Blue) vs 1.13V (Pink)：

Thanks in advance！

Best regards！

Jason

Jason

Can you disconnect the DP159 OE pin from the FPGA and add a pulldown capacitor to it? The OE pin already has an internal pullup resistor, and with external pulldown capacitor, this will create a RC time constant delay and you can vary the capacitor to change the delay time.

I am struggling to understand why DP159 would fail to response to I2C request. Have you tried different I2C address? Any chance you can have a 3.3V I2C controller that can be connected directly to DP159 to see if works?

Thanks

David 

Hi, David;

I have gone through the other three address, and they all not give out "ACK"

I will try to do it according to your suggestion (disconnect the DP159 OE pin from FPGA then add a PU capacitor) next week.

Many thanks for your great patience!!!

Best regards!

Jason

Jason

You want to add a pulldown capacitor on the OE pin. The capacitor value will impact the reset timing, you can start with a 0.22uF capacitor.

Thanks

David

Hi, David:

I have done according to below figure.20, and disconnect OE then add a 0.22uF pulldown capacitor on it. But I2C_CTL also don't work. I test power sequence between 3.3v/1.1v and OE. You can see that the timing requirement is meet completely. But the Level of OE is only ~2.3v.  Datasheet also explain that .

3.3V(red) vs OE(blue) during power on

1.1V(red) vs OE(blue) during power on

OE level requirement

Thanks in advance!

Best regards!

Jason

 David:

BTW, I2C_EN is pulled up with 64.9K according to reference design in datasheet in my schematic. I test I2C_EN pin, and its level is about 2.56v. But there is no level requirement in datasheet as below figure shown. This 2.56v level of I2C_EN is OK?

Thanks in advance!

Best regards!

Jason