XIO2001: leakage issue

Hi,

I am looking into this issue.  Please allow me some time to understand the problem.

Is there a functional issue caused by this leakage?

Regards,

Nicholaus

Hi Nicholaus

If the customer disconnects j11 at present, p3v3 will not leak electricity If the j11 is not disconnected, the p3v3sus will always have power, and the p3v3 will have 2.1v when it is turned off. This will affect the motherboard timing

Hi Gareth,

So, the system is trying to get into the L2 low-power PCIe state.  L2 is where the main 3.3V supply is turned off, but the 3.3V Auxiliary supply is on.

The problem is, while in L2, there is a voltage leaking into the main 3.3V supply which causes it to have a voltage of 2.1V. 

      1. The customer disconnects 3.3V Aux (J11) from the XIO2001, the main 3.3V rail is ~0V when it is turned off as it should be.

      2. The customer does not disconnect 3.3V Aux (J11) from the XIO2001, the main 3.3V rail will still be 2.1V when the main 3.3V rail is turned off.

Is it possible that item #3 in the errata is causing an issue here?  XIO2001 Errata (Rev. B) (ti.com)

Can you take a snapshot of the XIO2001 PCI Configuration space during these two conditions?  It will help to know the status of these registers:

Device Status Register (0x7A)

Control and Diagnostic Register (0xC8) 

Let me know if my understanding is incorrect.

Thanks,

Nicholaus

Hi Nicholaus

The customer connected the discharge resistor to p3v3, and it seems that the leakage problem did not happen. Our current configuration is only connected to xio2001 and not connected to any load-bearing devices. Is there a p3v3 discharge path inside xio2001? Can you provide a block diagram?

Thanks for your help

Hi Gareth,

Sorry, I cannot provide any IP-sensitive information on this public forum that is not in the datasheet.  I can test in the lab or reach out to design to see if this behavior is expected or not, but in order to do that I will need a clear understanding of the problem.  To that end, can you confirm my understanding of the issue from the previous post?

"So, the system is trying to get into the L2 low-power PCIe state.  L2 is where the main 3.3V supply is turned off, but the 3.3V Auxiliary supply is on.

The problem is, while in L2, there is a voltage leaking into the main 3.3V supply which causes it to have a voltage of 2.1V. 

      1. The customer disconnects 3.3V Aux (J11) from the XIO2001, the main 3.3V rail is ~0V when it is turned off as it should be.

      2. The customer does not disconnect 3.3V Aux (J11) from the XIO2001, the main 3.3V rail will still be 2.1V when the main 3.3V rail is turned off."

When you say the XIO2001 is not connected to any load-bearing devices, do you mean that the XIO2001 is connected to a root complex on the PCIe side, but there are no devices connected on the PCI bus correct?

Can you show me where the discharge resistor was placed in the schematic?

Thanks,

Nicholaus

Hi Gareth,

Are there any updates on this issue?

Regards,

Nicholaus