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DP83TC814R-Q1: Concern for the floating condition at TX pin during RMII operation mode

Kazuki Kuramochi
Genius 10605 points
Part Number: DP83TC814R-Q1

Hello expert,

I'd like to confirm about the risk of floating condition at TX pin during  RMII operation mode.

I had confirmed about similar point in the previous E2E thread.
I this thread we concluded that TX and RX pin want be floating during RMII operation mode.
After this E2E thread, I discussed about SoC team which use with this PHY and we found  the mode that will cause floating condition during RMII mode.

SoC require that PHY never cause floating(mid-supply potential) condition if SoC's MAC is enabled.
So we may need to start-up PHY before start-up SoC's MAC.
Therefore, there is possibility to happen floating condition on TX pin due to SoC MAC cannot drive this bus.

Then, is there any risk of happening floating condition on TX pin?

Thank you and best regards,
Kazuki Kuramochi

  • 0
    TI__Mastermind 19250 points

    Hi Kazuki,

    In RMII mode, only TX_D0, TX_D1, RX_D0, RX_D1 are used.
    I believe that rest of TX and RX signals are left floating on the board and not connected to SoC. So there will not be a problem for SoC functionality. This is also not a problem for PHY functionality.

    Regarding TX_D0, TX_D1, these signals should be connected and driven by SoC. Before SoC boots-up and drives, these pins are floating.
    This is a risk, but it is usually taken care by holding the device in RESET until SoC boots-up and drives these pins.

    Regarding RX_D0, RX_D1, these signals have internal pull downs. So the pin voltage is defined as soon as power supplies of the PHY are up.

    --
    Regards,
    Gokul.

  • 0 in reply to Gokul Koraganji
    TI__Genius 10605 points

    Hi Gokul-san,

    Sorry for late reply.

    For RX_D0/D1, as far as I understand, either or both pin require pull-up resistor to use PHY as RMII.
    Does it mean  that RX_D0/D1 pin will be mid supply condition before entering RMII mode?

    SoC's RX_D0/D1 cannot accept mid supply condition after enabling  receiver buffer.

    On the other hands, as you explained, TX_D0/D1 require specific timing for releasing nRESET.
    However, SoC side's TX_D0/D1 can accept floating condition.

    So I worried about initialization sequence regarding SoC and PHY.

    Thank you and best regards,
    Kazuki Kuramochi
     

  • 0 in reply to Kazuki Kuramochi
    TI__Mastermind 19250 points

    Hi Kazuki,

    If SoC TX_D0, TX_D1 can accept floating condition, then we need worry about and there is no need to sequence RESET_N.

    On RX_D0, RX_D1, the voltage will be minimum of 0.7*VDDIO when this strap is mounted. Since this value is higher than JEDEC VIH, I think this voltage should be okay for SoC.
    If the SoC is not okay with this voltage, then I suggest do the following

    1. Hold the RESET_N low initially
    2. Let PHY power-up and wait for at least 10ms
    3. Release the RESET_N
    4. Wait for 100us and enable the receive buffers of the SoC.

    Please let me know if this plan looks okay.

    --
    Regards,
    Gokul.

  • 0 in reply to Gokul Koraganji
    TI__Genius 10605 points

    Hi Gokul,

    Thank you for your reply.

    This is just confirmation but PHY's Tx pin will accept floating condition as far as SoC's Tx pin side accept floating condition.
    Is this correct?
    Also, would you tell me why PHY's Tx pin has concern for floating condition and relating Phy Tx pin's acceptance of this condition and SoC Tx pin's capability?
    I'm little bit confused about Tx pin's floating condition capability.

    And, I'd like to break down your recommended procedure.
    Is following my understanding correct?

    1. Hold the RESET_N low initially
    2. Power-up "PHY" and "SoC"
    3. Enable Tx output buffer on SoC to avoid floating condition on PHY's Tx side.
    4. Release the RESET_N to initialize PHY
    5. Wait for 100us and enable the receive buffers of the SoC to avoid mid supply condition at SoC Rx pin after enabling input buffer in SoC.

     

    Also, I'm looking forward your reply for my email.

    Thank you and best regards,
    Kazuki Kurmaochi

  • 0 in reply to Kazuki Kuramochi
    TI__Mastermind 19250 points

    Hi Kazuki,

    I'm on leave today. I'll get back to you by end of tomorrow.

  • 0 in reply to Gokul Koraganji
    TI__Genius 10605 points

    Hello Gokul,

    I appreciate your status update.
    I'm looking forward to hearing back from you tomorrow.

    By the way, this is just confirmation but SoC side may only accept 0.85*VIO from the view point of long term reliability.

    Thank you and best regards,
    Kazuki Kuramochi

  • +1 in reply to Kazuki Kuramochi
    TI__Mastermind 19250 points

    Hello Kazuki,

    You are right regarding TX_*. It is better if we enable TX_* buffers from SoC side before we can release RESET_N of the PHY.

    Kazuki Kuramochi said:

    Is following my understanding correct?

    1. Hold the RESET_N low initially
    2. Power-up "PHY" and "SoC"
    3. Enable Tx output buffer on SoC to avoid floating condition on PHY's Tx side.
    4. Release the RESET_N to initialize PHY
    5. Wait for 100us and enable the receive buffers of the SoC to avoid mid supply condition at SoC Rx pin after enabling input buffer in SoC.

    This routine is correct.

    --
    Regards,
    Gokul.