DS90UB949-Q1EVM: Can't select Enable Generator

Hello Sundar,

1) If you are selecting External timing or External Clock, make sure you have a video source connected at the input of the UB949. Otherwise, select Internal.

2) Also, if you change any parameter from the Video Control on the right-hand side, you have first to apply and then enable the Generator.

3) If still not working, make sure to connect ALP only to one device, not two as shown.

Hello Sundar,

The process for writing the EDID SRAM is as follows:

1) Set Reg 0x48[0] to enable APB. This bit should remain set through remainder of procedure. Reg 0x48[4:3] should be set to 01. If desired, the auto increment bit (Reg 0x48[2]) may be set to enable the auto-increment function.

2) Write to Reg 0x49 to set the 8-bit register address.

3) Write the 8-bit data to Reg 0x4B. The APB Interface write will occur once this register has been written.

4) If APB auto increment bit is set, the next register location may be written by repeating step 2, otherwise repeat steps 1 and 2 to write another register location.

Additionally, please refer to this Thread and this Thread.

On the UB949 EVM, you would need to connect your I2C to either I2C headers or to the DDC headers shown in the screenshot below.

1) Accessing EDID SRAM via I2C
• EDID SRAM data is accessible from the I2C interface on the device through an indirect register access mechanism provided by the APB Interface registers.
• The APB Interface registers consist of a control register (Reg 0x48), address registers (Reg 0x49, 0x4A) and data registers (Reg 0x4B – 0x4E).
• The address registers provide the byte offset to the EDID SRAM.
• When accessing EDID SRAM, only the first data register (Reg 0x4B) is used since the interface is 8-bits.
• For EDID SRAM accesses, Reg 0x48[4:3] should be set to a value of 01 to select EDID SRAM.

The process for writing the EDID SRAM is as follows:
1) Set Reg 0x48[0] to enable APB. This bit should remain set through remainder of procedure. Reg 0x48[4:3] should be set to 01. If desired, the auto increment bit (Reg 0x48[2]) may be set to enable the auto-increment function.
2) Write to Reg 0x49 to set the 8-bit register address.
3) Write the 8-bit data to Reg 0x4B. The APB Interface write will occur once this register has been written.
4) If APB auto increment bit is set, the next register location may be written by repeating step 2, otherwise repeat steps 1 and 2 to write another register location.

The process for reading EDID SRAM is as follows:
1) Write to Reg 0x49 to set the 8-bit register address.
2) Set Reg 0x48[1]. This will initiate the APB Interface read. Reg 0x48[0] must also be set during any write to reg 0x48, while the Reg 0x48[4:3] must be set to 01. If desired, the APB auto increment bit (Reg 0x48[2]) may be set to enable the auto-increment function.
3) Read the first APB data register (Reg 0x4B).
4) If APB auto increment bit was set, the next register location may be read by repeating steps 2 and 3, otherwise repeat steps 1-3 to read another register location.
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2) Reading EDID SRAM via DDC:
• The HDMI DDC interface is a simple I2C interface which allows access to the EDID information for an upstream HDMI Transmitter.
• After initialization, if the DDC interface is enabled, the 256-byte EDID structure can be read using the DDC interface directly.
• By default the EDID structure will be located at a slave address of 0xA0 (8-bit address). This address location can be changed by changing the value in Reg 0x51.
• By default the interface is read-only, but can be made writable by clearing bit 0 of Reg 0x51.
• The interface is a standard I2C slave interface capable at operating with Standard-mode or Fast-mode timing.
• The DDC interface to the EDID SRAM can be disabled by setting Reg 0x4F[0].

Sundar,

you can use UART but not for writing or reading EDID. This can be accessed only via I2C or DDC buses.

You can either connect your I2C USB2ANY or Aardvark tools to the I2C bus, or you can simply connect your PC via USB cable to the Mini-USB connector on the board and use the embedded MSP430 microcontroller to interface with the UB949.