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Original question:

NS16C2552: About the difference of the register.

NS16C2552: question about data transmitting and receiving procedure

Go
Genius 4220 points
Part Number: NS16C2552
Other Parts Discussed in Thread: TL16C2552

Hi,

According to the related thread, it seems that NS16C2552 needs to change transmit sequence from the sequence which is using on PC16552D.

Do you have any transmitting and receiving procedure that TI recommended for NS16C2552? it would be very appreciated if you have some documents that explain about the procedure.

and the related thread said TL16C2552 seems the same register map with PC16552D.
Does it mean that TL16C255 can use same data-transmitting and data-receiving procedure
that is used on PC16552D?

How is the interrupt cleaning behavior on TL16C2552?
Is that same as PC16552? or NS16C2552?

Thanks,

Go

  • +1
    TI__Mastermind 47338 points

    Hi Go,

    Go said:
    According to the related thread, it seems that NS16C2552 needs to change transmit sequence from the sequence which is using on PC16552D.

    From the previous thread, it looks like there was a difference in the interrupt sources and clearing. Whenever you read from the IIR register on the NS16C2552, INT would be cleared which is possibly why the NS16C2552TVS did not generate the next Tx Empty interrupt. 

    Go said:
    Do you have any transmitting and receiving procedure that TI recommended for NS16C2552? it would be very appreciated if you have some documents that explain about the procedure.

    We do not offer any source code to these devices. We usually only deal with hardware related issues for our devices. 

    Go said:
    and the related thread said TL16C2552 seems the same register map with PC16552D.
    Does it mean that TL16C255 can use same data-transmitting and data-receiving procedure
    that is used on PC16552D?

    This is what it seems from Bobby's comment 4 years ago. I would expect there are some similarities between these two devices as they have the same pinout and similar register maps. If you look at table II on the PC16552D datasheet and compare it with table 3 on the TL16C2552, they have same maps. I would assume that the data-transmitting and data-receiving procedure would be the same. Since the PC16552D is a device from 1995, it is possible there might be hiccups in the implementation between the two devices. 

    Go said:
    How is the interrupt cleaning behavior on TL16C2552?
    Is that same as PC16552? or NS16C2552?

    TL16C2552 - Table 5

    PC16552D - Table V 

    NS16C2552 - Table 8 

    These are the table numbers for the interrupt sources and how to clear the interrupt. They look to be similar in several ways, but there are some differences. For example, on the PC16552D, to clear a "receiver data available" or "trigger level reached" interrupt, you can read the receiver buffer register or the FIFO drops below the trigger level. For the TL16C2552, this is simplified by only reading the receiver buffer register.

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    Genius 4220 points

    Hi, Tyler

    Thank you for your comment.

    Regarding your comment below, 

    These are the table numbers for the interrupt sources and how to clear the interrupt. They look to be similar in several ways, but there are some differences. For example, on the PC16552D, to clear a "receiver data available" or "trigger level reached" interrupt, you can read the receiver buffer register or the FIFO drops below the trigger level. For the TL16C2552, this is simplified by only reading the receiver buffer register.

    I also checked  TL16C2552 - Table 5  and PC16552D - Table V , as you said there's no description about interrupt clear by "the FIFO drops below the trigger level " on TL16C2552 - Table 5.

    but I found the description on TL16C2552 D/S page24 as follows,

    "The received data available interrupt is issued to the microprocessor when the FIFO has reached its programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level."

    Does it mean that received data available interrupt on TL16C2552 also clear it by "the FIFO drops below the trigger level " same as PC16552D?

    Thanks,

    Go

  • 0 in reply to Go
    TI__Guru 74252 points

    Go,

    We will have a response to you by tomorrow end of business CST.

    Regards,

    Eric Hackett 

  • 0 in reply to Eric Hackett
    Genius 4220 points

    Hi, Eric

    Thank you for your support.

    We're waiting for your response.

    Thanks,

    Go

  • 0 in reply to Go
    TI__Mastermind 47338 points

    Hi Go,

    To your question above...

    Go said:
    Does it mean that received data available interrupt on TL16C2552 also clear it by "the FIFO drops below the trigger level " same as PC16552D?

    This statement seems to be true according to the datasheet. The TL16C2552 would have the same functionality just as the PC16552D. I don't know why that information was not in the table. 

    Regards,

    Tyler