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DS90UB948-Q1: Screen is only showing backlight when using pattern generator to set output.

Part Number: DS90UB948-Q1
Other Parts Discussed in Thread: ALP, USB2ANY

Hello all, 

I have been using DS90UB947TRGCRQ1 with DS90UB948-Q1 custom made boards. There were issues getting this combination to work so I attempted using patgen to create a screen image. The backlight is on but no image is showing up. 



The display parameter is as follows: 

		
display-timings { lvds1_timing_cct2nd12p3: CCT2nd12p3{ /*CCT 2nd 12.3" */ clock-frequency = <88000000>; pixelclk-active = <0>; de-active = <1>; hsync-active = <0>; vsync-active = <0>; hactive = <1920>; vactive = <720>; hback-porch = <16>; hfront-porch = <38>; vback-porch = <5>; vfront-porch = <8>; hsync-len = <12>; vsync-len = <3>; };

 

The code for pat gen: 

#/bin/bash 
declare -a address=(0x63 0x66 0x67 0x66 0x67 0x66 0x67 0x66 0x67 0x66 0x67 0x66 0x67 0x66 0x67 0x66 0x67 0x66 0x67 0x66 0x67 0x66 0x67 0x66 0x67 0x65 0x64)
declare -a __write=(0x01 0x03 0x02 0x07 0x80 0x08 0x07 0x09 0x2D0 0x04 0x80 0x05 0x07 0x06 0x2D0 0x0C 0x10 0x0D 0x05 0x0A 0x0C 0x0B 0x03 0x0E 0x03 0x03 0x31)
# get length of an array
length=${#address[@]}
 # use C style for loop syntax to read all values and indexes
for (( j=0; j<length; j++ ));
do
#  printf "Current index %d with value %s\n" $j "${address[$j]}"
#  printf "Current index %d with value %s\n" $j "${write[$j]}"
  printf "i2cset -y 0x2 0x2c %d %s \n" "${address[$j]}" "${__write[$j]}"
  i2cset -y 0x2 0x2c ${address[$j]} ${__write[$j]}
done

With using the patgen. The only difference I am seeing is the lock status pulling high with the internal clock being used.

Any feedback or solutions will be very appreciated. Thanks!
  • Hi Shivan, 

    Can you initially try local PG from the DES first to establish a baseline?

    What is the criteria for successful backlight? Is that dependent at all on the incoming video data to the panel, or should be on by default?

    Regards, 

    Logan

  • Hi Logan,

    I apologize I did not include enough info in initial post. I did try local PG from the Deserializer. The code you see above is the attempt for local PG from the Deserializer. 

    Backlight is independent of video data of the panel so it should be on by default. 

    Thanks,

    Shivam  

  • Hi Shivam, 

    Thanks for the additional details. 

    Okay - so local DES PG is what is not working. This is most commonly causes by incorrect video timing (PCLK setpoint, resolutions, sync polarities, etc) or other gross issues on the OLDI TX itself (assuming its not something down stream in panel itself). 

    Can you provide the schematic? Are you using single or dual OLDI? 

    Can you probe the OLDI CLKs to see if those values are correct and that the OLDI ports are enabled/outputing?

    Do you have a panel datasheet for reference?

    Regards, 

    Logan

  • Hi Logan, 

    1. I verified that the panel is working with our basic setup without the SER/DESER. 

    2. You can see the deserializer attached here Our current configuration is set up for single OLDI. 

    3. I probed the OLDI CLK. Currently reading at 6 MHz when PAT GEN is set to 70 MHz. The deserializer is not outputting a clean sine wave as seen in the          attached image. 

    4. Unfortunately we do not have a complete datasheet. This display is custom made and in the preliminary stages of production. The info included in my initial post on display timings is what we have and have been using for our basic setup without SER/DESER testing. 

    Thanks,

    Shivam

  • Hi Shivam, 

    Thanks for the additional information. Just to confirm - the above waveform is probing pins 36 and 37 on the DES? This waveform definitely seems atypical. Did you happen to get an output of any of the OLDI data lanes?

    This might not be possible, but curious if you have access to a USB2ANY or an Aardvark to attach to 948 I2C bus? There is ALP PG tab that can more easily program and adjust these values. 

    Actually, I see some concern with the script above. 0x66 and 0x67 are indirect registers to program the PatGen registers, but it looks like you are trying to send 0x2D0 (3 bytes) which isn't allowed. 

    Regards, 

    Logan

  • Hi Logan,

    Yes I can confirm that this is happening on pins 36 and 37. Even setting the clock divider to multiple values, I am failing to see a consistent frequency on the clock lines. There is no output on the other OLDI lines. 

    I do not have access to USB2ANY at the moment. 

    That was an error on my part. I double checked the script and it does reflect 0x2D. 

    Thanks,

    Shivam

  • Hi Shivam, 

    Can you provide the schematics so we can review those? Feel free to private message them to me. 

    If you download the ALP and 948 profile, you can actually still use demo mode and extract the correct register settings for various PatGen modes & CLK/timing modes. 

    Are you able to do a register dump of the actual written values also for further review?

    Regards, 

    Logan

  • Hi Logan, 

    Sorry for the delay. I received more details about the display horizontal and vertical display area. That change along with properly setting address 0x65 resulted in a successful PG from the deserializer. For the connection between the serializer and deserializer, there was a hardware issue on the serializer side, when resolved, successfully transmitted our desired image across. Thanks for the help!

    Shivam