SN65DSI86: Resolution Calculation

Jianing Zhu

Expert 4325 points

Part Number: SN65DSI86

Dear team,

Custome's application is 2880*1800, 24bit, @60Hz, pixel clock 652.26MHz, panel EDID.

Could you pls check if SN65DSI86 could support this application? Thanks!

2880 x1800 x 24 x 60 = 7.5Gbps < 1.5Gbps x 8lanes =12Gbps, so it could satisfy?

With PCLK of 652.26MHz, and 24bpp, the stream bit rate is 652.26x24= 15.654,

DSI CLK frequency = 15.654 / (2 x DSI lane). If using DSI lane of 4, DSI CLK = 1956.75MHz. ?

Thanks!

over 2 years ago

0 Allison Noe over 2 years ago

TI__Intellectual 1265 points

Hi Jianing,

Can you double check the pixel clock frequency spec? 652.26MHz seems high for this resolution.

Your calculations are correct. SN65DSI86 cannot support this application, as it cannot support the DSI CLK frequency. The DSI CLK can handle frequencies ranging from 40 to 755MHz. Even if all 8 DSI lanes were utilized, the necessary DSI CLK frequency could not be supported.

Thanks, Allison

0 Jianing Zhu over 2 years ago in reply to Allison Noe

TI__Expert 4325 points

Hi Allison,

The pixel clock 652.26MHz is from eDP panel spec. The panel could support 120Hz max. It's used on tablet.

Do we have any other suitable deivce? Thanks!

0 Allison Noe over 2 years ago in reply to Jianing Zhu

TI__Intellectual 1265 points

Hi Jianing,

Thank you for the clarification. We do not have another suitable device, SN65DSI86 is the only DSI to eDP bridge we offer.

Thanks, Allison

Interface

Interface forum

SN65DSI86: Resolution Calculation