TLK6002: Transmit underflow and overflow errors

Hi Mallikarjuna,

Your math looks correct.  Are you using 16 bit or 20 bit mode?  Is your TX_CLK synchronous with the parallel data input to the TLK6002?

Besides configuring half rate, is there any other configuration you have tried?

Thanks,
Drew

Hi Drew,

I am using 16-bit mode. My TX_CLK is synchronous to incoming Parallel Input Data and I have tried configuring in Quarter rate too but still the register is not reflecting and having the FIFO errors.

The value of register 0x05 is 0x61CB. Channel Sync is happening.

Thanks

Mallikarjuna

Hi Mallikarjuna,

A couple more questions:

Are you using the same clock for TXCLK and REFCLK, or do you have two separate 123 MHz clocks?  Do you have a buffer or clock driver that can drive LVDS/LVPECL REFCLK?

Regarding setting the rate via register 0x01, are pins RATE_A/B[2:0] set for software selectable rate?  Is ARS_EN[1:0] set to 2'b00?  Have you set PLL_MULT[3:] to 4'b1101?

Thanks,

Drew

Hi Drew,

No I am using same clock generator for TXCLK  and REFCLK.. I am driving the TXCLK from FPGA output clock buffer with required voltage standard.

I am using CDCM6208 clock generator IC for REF_CLK and TX_CLK.

Yes I have modified the pins to software selectable rate and ARS_EN is made to 2'b00.

PLL Value is  set to  0x0D.

Regards

Mallikarjuna B

Hi Mallikarjuna,

What differentiates this configuration from the configuration in the other thread where 0x05 does not have FIFO issues?

Thanks,
Drew

Hi drew

In the other thread I am working at 3.93 Ghz at FULL RATE as you can see from the above table. The TX_CLK IS 196.3 Mhz and REF_CLK is 122.88 Mhz

calculate from the given formula. The PLL value is also set as specified in the table.

While working at FULL RATE there are no issues. The only problem is we are unable to configure into HALF_RATE.

We tried using Hardware configuration too. Still the register 0x01 is reflecting 0x10D.

Thanks

Mallikarjuna

Hi Mallikarjuna,

It seems odd that both TX_FIFO_UNDERFLOW and TX_FIFO_OVERFLOW are being set.  Are these both consistently set, or is it sometime just one or the other?  If they are both consistently set, I'm wondering if that indicates a more substantial configuration issue as opposed to just a clock variation issue.

Regarding register 0x01, this is puzzling for half rate.  Are you saying that you set RATE_x[2:0]=3'b100, set register 0x01 to 0x015D, and read back 0x010D?

Note that 0x01[7:4] is only valid while RATE_x[2:]=3'b100, so if you select half rate mode with the rate pins, the register value is not valid.

Is this an SDR or DDR application?  Have you confirmed that the TLK6002 sampling/alignment matches your FPGA configuration?  See Figure 2-4.

Thanks,
Drew

Hi Drew,

1. No the TX_FIFO_UNDERFLOW and TX_FIFO_OVERFLOW are set continuously.

2.Yes while Writing I have written  0x15D to 0x01 register but while reading I am getting the value 0x10D.

    I have verified configuration again and RATE_X[2:0] is set to 3'b100.

3. It is an SDR application. The sampling alignment matches the FPGA configuration.

Thanks

Mallikarjuna B

Hi Mallikarjuna,

If you modify other fields within 0x01, such as PLL_MULT, are these fields persistent?

Is it possible to share a register dump of the non-reserved registers?  Are you able to share a schematic?  You can send over E2E DM so that it is not public.

Thanks,

Drew

Hi Drew

From the above attachment provided (Continuous rate SERDES configuration settings table ) it is given that for HALF RATE the RATE_SCALE should be taken as "1".

I have taken RATE_SCALE value as "0.5" for HALF_RATE and did the SERDES REF_CLK calculation

Eg: For 2.4576 Gbps I took  TX_CLK  as 122.88 Mhz

From the above formula provides I took RATE_SCALE as " 0.5 " SERDES_MULTIPLIER as " 20 "  I got REF_CLK as 61.44Mhz.

When I work with this configuration I have "ZERO" TX_UNDERFLOW and TX_OVERFLOW errors but still the 0x01 register is showing 0x10D( i.e Rate is not configured ) and even Channel Sync is happening.

The register 0x05 value is 0x600B.

.

But from the above table you can see for 2.4576 Gbps they have given REF_CLK as either 153.6 Mhz and 122.88 Mhz. while I have given 61.44Mhz

Can you correlate this behavior

Thanks

Mallikarjuna

Hi Mallikarjuna,

Thanks for the update, I'm looking into this.

Thanks,
Drew

Hi Drew

Is there any about RATE_SELECT issue ?

Regards

Mallikarjuna