Part Number: DP83TG720S-Q1
Dear Team,
We are considering TI's DP83TG720S-Q1 part for 1000 base T1 functionality in our product. We shall be interfacing with NVIDIA's Orin AGX SOM via RGMII interface.
The design guide for the Orin AGX doesn't contain any timing-related specifications (such as setup time, output skew etc). However, NVIDIA states that the Orin SoC complies with RGMII 2.0 standard. Furthermore, the SOM does not support the RGMII-ID feature and delay must be added externally by PHY or PCB. Orin_RGMII.pdf
Based on this data, we are considering the following approach.
Orin Tx out to PHY Tx inConsidering +/-500ps output skew as per the RGMII standard and minimum 1ns setup/hold time mandated by PHY chip, the required clock to data delay shall be greater than 1.5ns and less than 2.5ns (for 4ns ton). To meet this requirement, DLL DLL_TX_DELAY_CTRL_SL=8 or DLL DLL_TX_DELAY_CTRL_SL=9 shall be considered.
PHY Rx out to Orin Rx in
The Orin mandates a clock-to-data skew of greater than 1.5ns and less than 2ns to ensure proper sampling. The in-built delay values for Rx don't seem to meet this criterion. Having said that, we may have to add an external delay in the form PCB delay or clock buffer (on top of the PHY internal delay if used).
Can the TI team let us know if the above approach could be considered to satisfy RGMII timing at both ends?
Also, to meet RX timings, does adding a clock buffer for additional delay make sense? if so, can TI suggest a buffer part for the same?
