TMDS1204: FRL sources issue

Hello,

What are you all reading from register offset 0x20h?

Could you try using the I2C example script in the application note (link below) and see if you have any success?

Please see Section 3.1 example script in this document:

https://www.ti.com/lit/an/snla419/snla419.pdf?ts=1686752131279&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTMDS1204

Thanks,

Zach

Hello,

I read 0X0 from the register offset 0x20.

We don't use aardvark connector but I'll set the registers with the script values.

Thanks,

Khalid

Hello,

Let me know if you get a different result.

Also, are you using the DDC snoop feature (see datasheet section 8.3.2 DDC Snoop Feature)?

Thanks,

Zach

Hello Zach,

I apply the values of your script with the same result.

[vc.1:F45EAB39FE43]:~$ i2cset -y 14 0x5c 0x0a 0x08
[vc.1:F45EAB39FE43]:~$ i2cset -y 14 0x5c 0x0b 0x34
[vc.1:F45EAB39FE43]:~$ i2cset -y 14 0x5c 0x0c 0x71
[vc.1:F45EAB39FE43]:~$ i2cset -y 14 0x5c 0x0d 0xe2
[vc.1:F45EAB39FE43]:~$ i2cset -y 14 0x5c 0x0e 0x3f
[vc.1:F45EAB39FE43]:~$ i2cset -y 14 0x5c 0x10 0x00
[vc.1:F45EAB39FE43]:~$ i2cset -y 14 0x5c 0x12 0x13
[vc.1:F45EAB39FE43]:~$ i2cset -y 14 0x5c 0x13 0x01
[vc.1:F45EAB39FE43]:~$ i2cset -y 14 0x5c 0x14 0x13
[vc.1:F45EAB39FE43]:~$ i2cset -y 14 0x5c 0x15 0x01
[vc.1:F45EAB39FE43]:~$ i2cset -y 14 0x5c 0x16 0x13
[vc.1:F45EAB39FE43]:~$ i2cset -y 14 0x5c 0x17 0x01
[vc.1:F45EAB39FE43]:~$ i2cset -y 14 0x5c 0x18 0x13
[vc.1:F45EAB39FE43]:~$ i2cset -y 14 0x5c 0x19 0x01
[vc.1:F45EAB39FE43]:~$ i2cset -y 14 0x5c 0x1d 0xf3
[vc.1:F45EAB39FE43]:~$ i2cset -y 14 0x5c 0x1e 0x40
[vc.1:F45EAB39FE43]:~$ i2cset -y 14 0x5c 0x20 0x00
[vc.1:F45EAB39FE43]:~$ i2cset -y 14 0x5c 0x09 0x00


[vc.1:F45EAB39FE43]:~$ i2cget -y 14 0x5c 0x20
0x00
[vc.1:F45EAB39FE43]:~$ i2cget -y 14 0x5c 0x31
0x30
[vc.1:F45EAB39FE43]:~$ i2cget -y 14 0x5c 0x35
0x00
[vc.1:F45EAB39FE43]:~$ i2cget -y 14 0x5c 0x41
0x00
[vc.1:F45EAB39FE43]:~$ i2cget -y 14 0x5c 0x50
0x80
[vc.1:F45EAB39FE43]:~$ i2cget -y 14 0x5c 0x51
0x41
[vc.1:F45EAB39FE43]:~$ i2cget -y 14 0x5c 0x15
0x01
[vc.1:F45EAB39FE43]:~$ i2cget -y 14 0x5c 0x17
0x01
[vc.1:F45EAB39FE43]:~$ i2cget -y 14 0x5c 0x19
0x01

I have only changed the values of the following registers:
- register 0xa, 0x8 instead of 0x88 because we are not in lane swap configuration
- register 0xd, 0xe2 instead of 0xa2 (use ac-coupled), If I set the value 0xa2, I get nothing at the output, contrary to the value 0xe2.

But I still get the value 0x30 in register 0x31 instead of 0x34.

With DDC feature I get the same result

Thanks,
Khalid

Hello, Khalid,

How were you originally configuring your device? Could you share your schematic with me so I can understand the set up?

Does your FPGA require a separate CLK input or does it take in the embedded clock?

Have you tried register 0D->62? (Limited mode)

Please change the following registers to:

09->02, 0A ->0A, 0E-> BF and 10 ->03.

Thanks,
Zach

Hello Zach,

See attached the schematic.
The FPGA uses the embedded clock for FRL sources of course and a separate clock (TMDS clock) for non FRL sources
I tried it the limited without success, and also I tried the values that you sent me with the same result.

Do you have the documentation of the register 0x10?

Schematic_tmds1204_230615.pdf 

Thanks,

Khalid

Hello, Khalid,

Have you ensured that the HDMI source is HDMI 2.1 capable?

Do you have a DDC decoder that would monitor the DDC lanes? Can you send me the scope shots of that DDC decoder so I can take a look at the DDC traffic?

Thanks,

Zach

Hello Zach,

Sorry for this delay because I was on vacation.

I have the problem with both the HDMI2.1 pattern generator and the PC (Radeon Graphic card hdmi2.1) when are connected to the TMDS1204, and both display correctly up to 8K60 on the Samsung TV.

See attached for monitored DDC when the pattern generator hdmi2.1 is connected to TMDS1204.

Thanks and best regards,

Khalid

I2c_transcations.csv

Hello, Khalid,

We are reviewing the data that you sent to us and will get back with you shortly.

Thanks,

Zach

Hello, Khalid,

The I2C transactions document shows that there is a request for training patterns from registers 41 and 42, but sink does not present a pattern to change FFE or change data rate. The sink needs to write to registers 41 and 42 so the source will understand the pattern being requested.

Thanks,

Zach

Hello Zach,

I'll check it and let you know.

Thanks,

Khalid

Hi Zach,

I don't think this is the source of the problem, as the same FPGA design (same hdmi 2.1 sink) works with the eval board, which uses a different DS125MB203 redriver.

Thanks,

Khalid

Hello Zach,

I can understand this I2C transaction problem, but what I don't understand is why the same source works with the same sink using a different Ti redriver DS125MB203 component. See attached file
Maybe there's another problem.

hdmi21.pdf

Thanks & best regards,

Khalid

Khalid

Can we take a look both the DS125MB203 and TMDS1204 schematic?

Thanks

David

Hello David,

Please send me your email address so that I can send them to you privately, as they are confidential.

Thank you for your understanding.

Khalid

Khalid

I understand, please accept my friendship request so you can send me the schematic in a private message.

Can you also capture the DDC log file with the DS125MB203? 

Thanks

David

Hello David,

You can close it, thank you!

Best regards,

Khalid