TCAN4550-Q1: About CLKIN single-ended mode detection

Hello teritama,

No, there is no status register or indicator outside of SPI or CAN communication errors to know if the device has switched to single-ended outside of direct observation of the waveforms on the OSC1 or OSC2 pins. 

From your description of the errors and the Cin, Cout, and Rd components, I would say that the cause of the errors are almost certain to be caused by the device switching to single-ended clock mode.  See the TCAN455x Clock Optimization and Design Guidelines application note for additional information.

Likely the 2pF caps were likely recommended to optimize the frequency and a Rd=0ohm was likely recommended to improve the negative resistance.  However, this recommendation obviously did not consider the single-ended clock detection circuit requirements and therefore we need to adjust the component values to ensure stability and reduce the errors.

Increasing the load capacitors and or the series dampening resistor Rd between the OSC1 pin and the crystal will resolve the errors if set correctly.

Regards,

Jonathan

Hello Jonathan,

Thank you for your reply. We checked the crystal matching report. The waveform seems to be lower the threshold of single-ended clock mode.

In the application note, the waveform low level should be over 0.4V. How much you recommends the margin of low level? Is it okey that is 0.4V? 

We think the signal on OSC2(input)'s requirement is below.

 Amplitude: 1Vp-p ± **V
 Amplitude minimum voltage level: 400mV min.?
 Damping resistance Rd(OSC1 side):50 to 100Ω
 Oscillation safety factor Rsafety: 3 to 5 times of load resistance.

Is there other requirement or reference point on OSC2 or OSC1?

Best regards,

teritama

Hello teritama,

The 400mV level in the application note is actually a bit high and I need to revise the document to reflect some additional simulation and test data collected since this application note was drafted.  The abs max single-ended mode detection comparator threshold is 150mV across process, voltage, and temperature corners.  We do recommend some margin above this threshold to accommodate component tolerance and other variables in the system that may drift with PVT, but 400mV may not be achievable, nor is this much margin "required."  Adjusting the components such that a low level of 400mV may prevent the safety factor requirements from being achieved with some crystals.

Instead we are now recommending that at least 100mV of margin above the abs max (150mV) should suffice.  Therefore the low level should be at least 250mV if possible.

The detection comparator was designed to check for a DC voltage condition at startup, but we know that if the voltage on the OSC2 pin gets too low during oscillation that a mode change can occur. 

With an oscillating voltage, the signal can quickly and repeatedly drop below the detection threshold, and then above the threshold without causing a mode change.  There is some filtering created by the internal resistance and capacitance, as well as some response time for the circuit.  Because the signal's voltage is above the threshold for the majority of the time, the lowest peak level actually needs to drop below the detection threshold long enough for the circuit to change modes before the voltage rises above the threshold. 

This can mean that the lowest peak voltage of the OSC2 oscillation waveform can actually be lower than the limit without causing a change, and this has been observed and this too creates some small margin.  But it is very difficult for us to determine exactly when a mode change will occur and therefore we recommend adding the margin to the DC level to prevent any possibility of a mode change from ever occurring. 

The margin created with a 400mV level would certainly prevent a mode change, but as I've noted, the margin created from 250mV provides 100mV to the worst case, and 250mV to the typical DC levels which should exceed any drift from component tolerance and PVT drift.

Regards,

Jonathan

Hello jonathan,

The customer start to design that low level is above 250mV. About clock amplitude, in the application note says nominally 1Vpp.

Is there some requirement for amplitude ex. maximum limit or minimum limit? 

Best regards,

teritama

Hello teritama,

The Automatic Gain Control (AGC) and Peak Detection circuit will try to adjust the current sourced to the crystal through the transimpedance amplifier so that the peak-to-peak amplitude of the oscillation is approximately 1Vpp.  There is no maximum specification for this parameter.  However it is possible that the Vpp amplitude can exceed 1Vpp even when the AGC has adjusted the amplifier to the minimum level.  In this situation the lowest peak level can become close to the single-ended clock mode detection threshold which is what we want to avoid by adjusting the capacitor and series dampening resistors to optimal values.

Regards,

Jonathan

Hello Jonathan,

The customer is selecting damping resistance and they measured OSC2 voltage waveform using 75ohm to 120ohm condition.

The oscillation amplitude is changed 1020mV(Rd=75ohm) to 892mV(Rd=110ohm) range. Is this range is acceptable?

When using this resistance, OSC2 signal low level was 152mV to 256mV. We will comment to customer to select the resistance that low level is over 250mV.

In addition, in application note "Verify the magnitude of the negative resistance is 3 to 5 times larger than the Load Resistance by the following formula.".

In my understanding, typically this margin is 5 times lager than load resistance. Why is this 3 to 5 times in this application note? 

Best regards,

teritama

Hello Teritama,

The OSC2 low voltage is the most critical factor and the detection threshold has a max value of 150mV across process, voltage, and temperature conditions.  We recommend at least 100mV of margin to this threshold to account for possible component tolerances and capacitor de-rating, etc.  Therefore if the min voltage of OSC2 can remain at 250mV or higher, this should have the needed margin.

There are several "typical" understandings for what the safety factor margin should be depending on who you ask.  3-5 is a common range, you feel it should be 5, and others feel it should be 10.  Optimizing the circuit requires balancing all of the parameters where improvements to one parameter comes at the expense of another parameter.  Therefore, the greatest margin that can be achieved while satisfying the other parameters should be the goal. 

Regards,

Jonathan

Hello Jonathan,

I made sense how to thinking. Thank you so much.

The customer is thinking use below oscillator as the second plan.

https://www.ndk.com/en/products/upload/lineup/pdf/NDKT01-00005_en.pdf

When use this oscillator, I think this device has to be used single-ended mode. Do you have any case in which this type of oscillator is used?

In my understanding, when used in single-ended mode OSC2 pin must be connected GND and amplitude of OSC1 clock is reference VIH and VIL in datasheet.

If there is other requirement, let me tell.

Best regards,

teritama

Hello Teritama,

Yes, this oscillator looks like it would work, assuming it is of a correct frequency for CAN such as either 20MHz or 40MHz.  I understand most crystal and oscillator datasheets specify a single frequency for a family of devices, but can be produced for a range of frequencies.  But the voltage and signal level parameters look they are acceptable.

To use a single-ended clock such as this, you will need to ground the OSC2 pin and then the clock signal output of the oscillator is connected to the OSC1 pin of the TCAN4550-Q1with reference levels of VIH and VIL as specified in the datasheet.  Generally speaking the oscillation voltage swings between VIO and GND.  So you are correct in your understanding.

Best Regards,

Jonathan