DP83822I: CPSW RMII connects to DP83822 but cannot ping to PC

Hi PHY Team Experts,

This RMII PHY DP83822 is in master mode, & we have used oscilloscope to check the clock frequency is 50MHz.

We have dumped the phy registers value from address 0x0 to 0x1f in DP83822 shown below. Could you please provide some suggestions about it? Thanks!

root@j784s4-evm:~/mcu_cpsw2g# ./mdio_reg_dump.sh  
page: 0 reg: 0 val: 0x3100
page: 0 reg: 1 val: 0x786d
page: 0 reg: 2 val: 0x2000
page: 0 reg: 3 val: 0xa240
page: 0 reg: 4 val: 0x05e1
page: 0 reg: 5 val: 0xcde1
page: 0 reg: 6 val: 0x000f
page: 0 reg: 7 val: 0x2001
page: 0 reg: 8 val: 0x4006
page: 0 reg: 9 val: 0x0000
page: 0 reg: 10 val: 0x0100
page: 0 reg: 11 val: 0x1000
page: 0 reg: 13 val: 0x401f
page: 0 reg: 14 val: 0x1000
page: 0 reg: 15 val: 0x0000
page: 0 reg: 16 val: 0x0615
page: 0 reg: 17 val: 0x0108
page: 0 reg: 18 val: 0x6400
page: 0 reg: 19 val: 0x2800
page: 0 reg: 20 val: 0x0000
page: 0 reg: 21 val: 0x0000
page: 0 reg: 22 val: 0x0100
page: 0 reg: 23 val: 0x0065
page: 0 reg: 24 val: 0x0400
page: 0 reg: 25 val: 0xbc22
page: 0 reg: 26 val: 0x0000
page: 0 reg: 27 val: 0x007d
page: 0 reg: 28 val: 0x05ee
page: 0 reg: 30 val: 0x0102
page: 0 reg: 31 val: 0x0000

Kind Regards,

Kevin

Hi Kevin,

Please let me review your comments and get back to you.

Regards,
Rahul

Hi Rahul,

Thank you! Customer also provides the DP83822 checklist below.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/DP83822_5F00_Schematic_5F00_Design_5F00_Review_5F00_Checklist_5F00_Customer.xlsb

Kind Regards,

Kevin

Thank you for sharing the checklist Kevin.

Regards,
Rahul

Hi Kevin,

Can you please share the register value of 467h, 468h ? These are in extended register space, please use the mmd register/ read write sequence mentioned in the datasheet.

Also reading Reg 17h, 0x0108 I noticed that bit 5 is 0 (MII mode of operation).

Can you please make sure PHY is in RMII mode ?

Kevin Peng said:

At the same time, we may need your help to check if the internal delay values being used and the properties being set are correct and will work with 100mbps full duplex link.

+       mcu_phy2: ethernet-phy@2 {

+               reg = <2>;

+        rx-internal-delay-ps = <1>;

+        tx-internal-delay-ps = <1>;

+       };

+};

This is used to adjust delays in RGMII not in RMII, which registers are being written in this device tree implementation to adjust the delay ?

Regards,
Rahul

Hi Rahul,

Thanks for your reply.

The index of the reg we provided is based on decimalism. So for 0x17, it should be reg index 23, and it has value 0x0065.

We will follow your suggestions to provide the data.

May I know that if there is any reference to adjust the delay in RMII?

Kind Regards,

Kevin

Hi Rahul,

We have an online debugging session today internally, there are 3 findings that may need your expertise to confirm. Thanks!

1: After trying ping to PC & some phy register reading, we found out that bit 11 & bit 6 in 0x0010 become 1. I am not sure if this indicates any problems?

2: Customer is configuring RMII master signaling, so using MAC interface configuration 010 below (25Mhz reference clock). They are also using the advertised mode. So may I know if RMII master signaling can work in advertised mode?

3: Currently if connect Reset from SoC to PHY, the 50MHz REF_CLK outputs incorrectly, now we only use power-up RC reset, disconnect the reset from SoC to PHY, which means there is no hot-reset for PHY. May I know if there will be any problem in PHY without having hot-reset?

4: We are trying to read register value of 467h, 468h, but it seems we could not get the values as we did for 0x0-0x1f, could you provide the method to read the register value of 467h, 468h?

Thanks,

Kevin

Hi Kevin,

Kevin Peng said:

1: After trying ping to PC & some phy register reading, we found out that bit 11 & bit 6 in 0x0010 become 1. I am not sure if this indicates any problems?

The false carrier sense latch bit in register 0x10 is set to 1 whenever a false carrier event has occurred, which essentially means there was a packet error.
The remote fault bits of the base page are used to transmit link fault and error information to the link partner

Kevin Peng said:

2: Customer is configuring RMII master signaling, so using MAC interface configuration 010 below (25Mhz reference clock). They are also using the advertised mode. So may I know if RMII master signaling can work in advertised mode?

Yes, RMII master should be able to advertise all required modes.

Kevin Peng said:

3: Currently if connect Reset from SoC to PHY, the 50MHz REF_CLK outputs incorrectly, now we only use power-up RC reset, disconnect the reset from SoC to PHY, which means there is no hot-reset for PHY. May I know if there will be any problem in PHY without having hot-reset?

This is interesting, how is the RESET of the PHY connected to SoC effecting the 50MHz REF_CLK ?

Without Reset to the PHY, if the SoC is turned off or in a different mode, 50MHz Ref Clock will always be supplied.
Reset is mainly used during the power-up sequence and also to hold the PHY in Reset until a stable XI input is supplied.

Kevin Peng said:

4: We are trying to read register value of 467h, 468h, but it seems we could not get the values as we did for 0x0-0x1f, could you provide the method to read the register value of 467h, 468h?

Here is an example to access Register 467h:

1. Write the value 0x001F to register 0x000D.

2. Write the value 0x0467 to register 0x000E.  

3. Write the value 0x401F to register 0x000D.

4. Read the value of the register 0x000E

-----------------------------------

While performing the ping tests, can customer use a network analyzer tool like Wireshark and verify if any packets are being transmitted from the PHY ?

Is customer also able to probe using a scope and verify if any communication is happening on the RMII lines ?

Regards,
Rahul