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TCAN4550EVM: Rx FIFO 0 overflow error

Expert 1940 points
Part Number: TCAN4550EVM
Other Parts Discussed in Thread: TCAN4550


My setup has a thingy53 connected to TCAN4550 EVM using a bunch of connectors.

I followed the software demo code and was able to establish SPI communication, there by successfully configuring all the settings on TCAN4550 part.

It looks like I am able to send and receive can messages, but after some random time, I am seeing that the rx fifo 0 overflows and the interrupts halt.

I only setup Rx FIFO 0 with element size 64 and number of elements 64. Rx FIFO 1 and Rx Buffer are all set to 0(number of elements).

I have the FIFO 0 configured in overwrite mode. When the FIFO 0 is full, I can see that RF0F interrupt is set.

Do I need to enable watermark setting and make sure that it never sets the FIFO 0 full interrupt?

What exactly is expected once a set watermark level is reached?

Is there any document that explains this in more detail?



  • Hello GT,

    It sounds like the messages are being received faster than the MCU can read them and clear the FIFO.  The MCU can either poll for new messages, or set up an Internet Service Routine to read and clear the messages when they have arrived. You can monitor the new message bits to respond every time a new message has arrived, or you can monitor the watermark bits to allow the MCU to only read the messages after a certain number have arrived.  The decision comes to how frequently the MCU needs to be interrupted to read messages.  If you use the watermark method, you will need to set the watermark low enough to allow the MCU time to read and clear the messages from the FIFO before enough new messages will be received and completely fill the FIFO.  Therefore you will need to determine this based on your application.

    You can also directly check the FIFO status registers to determine the fill level and get/put address values and respond accordingly.

    There are two documents that I will refer to you for additional information.  The first is the TCAN45xx Software User's Guide that is a high level overview of how to configure and use the TCAN4550 device. 

    The second document is the M_CAN User's Manual developed by Bosch for their CAN FD Controller IP that is included in the TCAN4550.  Not all of the information on the MCAN controller could be duplicated in the TCAN4550 datasheet, so this document should be considered as a supplement document to those created by TI.  The only difference that needs to be noted is that the TCAN4550 has added an offset of 0x1000 to each register associated with the MCAN IP.  For example, the Control Register has an address of 0x18 in the MCAN User's Manual and an address of 0x1018 in the TCAN4550 device.



  • Hi Jonathan,

    Thanks for the response. I will take a look at the document and also follow through some of the suggestions here.

    One thing I have noticed on the TCAN4550 EVM, there is a red nINT LED, which continuously blinks when I am getting interrupts and just remains solid, when the issue happens. If I toggle the nINT LED switch on switch S4, it looks like the interrupt starts working again and I am able to read rx FIFO 0 again. Although, I am ending up in the same state with interrupts halting(solid red) after running sometime. All this in the same power cycle.

    Why does the position of the switch effecting the nINT line? Is this expected? I am just trying to rule out any hardware suspicions on my side.


  • Hi GT,

    The switch simply isolates the LED from the nINT net of the TCAN4550 device and the J16 Interface header.  Toggling it should have no impact on the TCAN4550's interrupt register and it won't clear the bits.  The nINT pin is the Global Interrupt pin for all enabled interrupt bit fields and is the logical OR of all faults that are not masked in registers 0x0820 and 0x0824 (which is a read only copy of register 0x1050). 

    When an interrupt bit is set, the nINT pin should pull low and remain low until the interrupt bit field is cleared through a write to the bit field through the SPI bus.  It may remain low if multiple interrupt bit fields are set at the same time and it will only get pulled high when all interrupt bit fields have been cleared.

    Monitor the Status Register 0x000C, the Interrupt/Diagnostic Flag 0x0820, and MCAN Interrupts register (either 0x0824 or 0x1050).  The MCAN Interrupts must be cleared by writing to register 0x1050 and not 0x0824, but it may be more convenient to read all interrupts with a single 2-register read of registers 0x0820 and 0x0824 by setting the Length field to 2 in the SPI read.

    Writing all set interrupt bits should clear the nINT pin allowing it to get pulled High again.



  • After debugging further, it looks like my issue is not that the buffer is overflowing, I have the overwrite register bit enabled and in general I am not seeing issues with buffer overflow.

    However, I am seeing that sometimes, even after clearing MCAN registers and reading rx fifo 0, I am not seeing any interrupt generated by nINT pin. Is there any limit on the frequency of MCAN interrupts. I feel like I might be missing interrupts even after clearing MCAN interrupts. When this issue happens, nINT line is held low(active low) and if I explicitly clear MCAN interrupt registers, nINT starts generating interrupts again. This doesn't happen at low CAN bus loads, but seem to happen as I increase CAN bus load.

    Any thoughts on what might be happening here?


  • The nINT pin is the logical OR of all device interrupts, so it will remain low if there is one or more interrupt bits still set.  Therefore, if the CAN message rate increases, new messages may have arrived while you are processing messages which may generate new interrupt bits that will keep the line low.

    At the end of your interrupt service routine, you should re-read the RX FIFO Status and Interrupt registers to see if there is still unread messages or interrupt bits that need to be processed and cleared.

    The MCAN controller IP allows for 2 separate Interrupt Lines and you can assign different interrupt bits to the different lines. The GPO2 and GPIO1 pins can be used as additional MCAN Interrupt Lines that would allow you to isolate certain interrupt bits such as the RX FIFO New Message bit so that it can be monitored independently instead of grouped into the global nINT line.