• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 34 subscribers
  • Views 2194 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

DP83869HM: TXD[3:0] & RXD[3:0] 11ps skew requirement (RGMII) in layout guidelines datasheet (pg. 113)

DP83869HM: Skew / Length matching requirement TXD[3:0] & RXD[3:0] (11ps / 60mil) in RGMII layout guidelines datasheet (pg. 100)

JW
Prodigy 30 points

Part Number: DP83869HM

I have a question about the information written in the datasheet (pg. 100 : 12.1.1.1.2 RGMII Layout Guidelines).

The datasheet gives a specific requirement about the length matching of the TX and RX data lines. My first thought was this matching requirement (66ps) is rather tight. 

Is there any well-founded explanation possible here? In my opinion with 1G RGMII the databus skew is more likely to be around a few hundred ps.  

I am looking forward to some calculations about the timing requirement here Slight smile


Thankyou!
  • 0
    TI__Mastermind 26165 points

    Hi,

    We recommend less than 11ps or 60 mils mismatch for high tolerance on RGMII interface. I do think less than 60mils mismatch between each of the RGMII traces are reasonable scale in PCB design. If you want have a higher mismatch between RGMII traces, it put more constraint on Microcontroller and the PHY side.

    --

    Regards,

    Hillman Lin

  • 0 in reply to Hillman Lin
    Prodigy 30 points

    Hi,

    But is there any explanation / calculation here? I my opinion a mismatch more than 60 mils is still acceptable?

    Delay in FR4 is about ~70ps/cm. 
    Using this information and the timing of 1G RGMII I don't see how matching of max 11ps is critical. 
    Since rise/fall times are 750ps. When the TXC is shifted with 2ns regarding to data.

    I think the window to clock in my data is large, in the ns range. See image        
    Yep not in the real world... but 1,75nS before my data gets clocked is a lot. What if due to signal integrity there is a safe space of about 500ps to get my data ready to clock in, why is the limit in layout set to 11ps… this is still just a fraction? 

    Can you show me any specification or calculations to prove 11ps is a limit?


    Thankyou,

    JW

  • 0 in reply to JW
    TI__Mastermind 26165 points

    Hi,

    Less than 60 mils mismatch is a recommended value for the layout. It is only the soft rule of thumb. I will reach out internally for further clarification.

    --

    Sincerely,

    Hillman Lin

  • 0 in reply to Hillman Lin
    Prodigy 30 points

    Hi,

    Thankyou! I look forward to the answer Slight smile

  • 0 in reply to JW
    TI__Mastermind 26165 points

    Hi JW,

    We will get back to you once we have more information.

    --

    Regards,

    Hillman Lin