SN65DP159: SN65DP159 & TPD5S115YFFR circuit review for HDMI 2.0 TX

Hello, Chiu,

1. Please rotate the schematic so that I can review.

2. The HDMI specification limits the DDC bus capacitance to ≤ 50-pF for both an HDMI source and sink. Therefore, care must be taken to make sure the total capacitance of all components (TMDS1204, FR4 trace, ESD, source, and sink) is less than 50-pF. Please refer to the specification Cb_LV or Capacitive load for each bus line on LV side found in 6.6 Timing Requirements. 

Cbus refers to the total load capacitance for each bus line (DDC and local I2C pins) contributing to the maximum load capacitance allowed on the entire I2C link not just at the connector output of the source or sink.

Thanks,

Zach

HI Dryer:

Thank you for your reply^^

 item 1 -->Thank you . If you have any concern Please let me know.

I want to know what is the  item 2 for DP159 DDC capacitors?(DP159 datasheet I can't find relevant information)

Is there any information that can be refer?

Thank you a lot. ^^

Hello, Chiu,

What is your application?

item 1: Please resend the schematic. Please rotate the schematic before resending.

item 2: You can refer to Figures 8-5 to 8-7 for references on how to configure the DDC lines for source side applications.

Thanks,

Zach

HI Dryer: 

item 1 : I have regained SCHEMATIC and have rotated.6740.hdmi_2.0_dp159_TX_OUTP_OK.pdf

item 2 : We can't find Figures 8-5 to 8-7 from SN65DP159 DataSheet ,We want to know SN65DP159 DDC parasitic capacitance? (?PF),

because the HDMI standard needs to be less than 50pf.

thank you!

Hello,

item 1: Please allow for 2 - 3 business days for me to review your schematic.

item 2: In section, 7.8 AUX, DDC, and I 2C Electrical Characteristics, of the datasheet the specification for Cio or input capacitance is 10 pF typical.

Thanks,

Zach