Dear TI experts,
Our project use DS250DF230 as retimer. We plan to use the internal PRBS function to test the design. Here is the connection loop:
FPGA --> channel 1 Rx
channel 1 Tx --> channel 0 Rx (with SFP module loopback)
The refence clock is 25Mhz. And FPGA generate 10.3125 Gbps clock signal to the channel 1 Rx. After setting the Low level page registers, both channel 0 &1 can detect the signal and locked.
Then go to High level page and enable the channel 1 PRBS function as below picture:
Then the channel 1 Post-Lock Output change to PRBS Generator:
Then the channel 0 can detect signal but can not lock it. As my understanding, PRBS signal should be also 10.3125 Gbps and can be locked by retimer. Could you give some suggestions how to generate the right PRBS signal? Thanks
Here is channel 1 CDR lock register read data:
0x02 -->D8
0x27-->1C
0x28-->B8
0x78-->30
0x8F-->80
