DS90UB941AS-Q1: How to increase the Backchannel bandwidth for i2c

The above video is broken.
Here is the new one.

DS90UB948-i2c-touch:

Native i2c touch:

Hi Joe,

I need to know more information about your system:

1. Provide the system block diagram?
2. What is the BC rate?
   1. Does increasing the BC rate improve the system?
3. What is the I2C bus speed?
4. Can you provide the I2C bus saleae capture when the screen is working properly and when the screen is lagging?

Best Regards,

Gil Abarca

1. Provide the system block diagram?
   =>
   
   
2. What is the BC rate?
   1. Does increasing the BC rate improve the system?
      => This is the question asking about.
      Which reg(s) can check the BC rate? Here is my regs:
      DS90UB941:
      No size specified (using byte-data access)
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 18 00 00 9a 00 00 58 54 54 01 17 00 67 30 00 00    ?..?..XTT??.g0..
10: 00 00 00 cb 00 00 fe 1e 7f 7f 01 00 20 00 01 00    ...?..?????. .?.
20: 0b 00 25 00 00 00 00 00 01 20 20 a0 00 00 a5 5a    ?.%.....?  ?..?Z
30: 00 b9 00 05 0c 00 00 00 00 00 00 00 00 00 81 02    .?.??.........??
40: 10 94 00 00 00 00 00 00 00 00 00 00 00 00 00 8c    ??.............?
50: 36 00 00 00 02 00 00 02 00 00 d9 21 07 06 44 44    6...?..?..?!??DD
60: 22 02 00 00 10 00 00 00 00 00 00 00 00 00 20 00    "?..?......... .
70: ac 00 00 00 00 00 00 ac 00 00 00 00 00 00 7f 00    ?......?......?.
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 82 00 78 00 21 65 40 00 00 00 00 02 ff 00    ..?.x.!e@....?..
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 82 00 68 08 21 00 00 00 00 00 00 02 00 00    ..?.h?!......?..
f0: 5f 55 42 39 34 31 00 00 00 00 00 00 00 00 00 00    _UB941..........

      DS90UB948:
      No size specified (using byte-data access)
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 58 04 00 f8 fe 1e 00 18 54 ac 00 00 00 00 00 00    X?.???.?T?......
10: 54 ac 00 00 00 00 00 00 00 01 00 00 03 19 99 09    T?.......?..????
20: 00 00 40 28 08 00 83 84 01 00 00 00 00 00 00 00    ..@(?.???.......
30: 00 00 90 25 02 00 00 9a 00 00 00 0f 20 e0 23 00    ..?%?..?...? ?#.
40: 43 03 03 00 60 88 00 00 0f 62 00 08 00 00 63 00    C??.`?..?b.?..c.
50: 03 10 00 01 80 00 08 00 00 7f 20 20 18 00 00 00    ??.??.?..?  ?...
60: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00    ....?...........
70: 00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00    ...???......?...
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 84 00 00 00 00 00 00 00 00 00 00 00 00 00    ..?.............
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00    ........?.......
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
f0: 5f 55 42 39 34 38 00 00 00 00 00 00 00 00 00 00    _UB948..........
      
      
3. What is the I2C bus speed?
   =>400k
   clock-frequency = <400000>;


4. Can you provide the I2C bus saleae capture when the screen is working properly and when the screen is lagging?
   => Here is the files videos and sals.
   Native touch connector shares the same i2c with FPD touch connector.
   "Native touch" means the panel is NOT pass through the FPD-LINK, using Native touch connector, and FPD-LINK is disabled.
   "FPD touch " means the panel is pass through the FPD-LINK, there is no panel on Native touch connector.
   FPD signals are measured on deserializer(948) side, while Native signals on serializer(941, the same pins on Native touch.)
   In FPD-LINK mode, Native IRQ is the REM_INTB of FPD IRQ
   
   Native touch flow is written below:
   A. panel(0x2a) reports "Native IRQ" when touching it.
   B. driver gets "Native IRQ" and send "0x27 0x00" to "Native i2c".
   C. panel send 66-byte of current touch frame to "Native i2c".
   
   FPD touch flow is written below:
   A. panel(0x2a) reports "FPD IRQ" when touching it.
   B. FPD-LINK set "Naitve IRQ" as the remote of "FPD IRQ"
   C. driver gets "Naitve IRQ"and send "0x27 0x00" to "Native i2c".
   D. FPD-LINK pass the i2c signal to "FPD i2c".
   E. panel send 66-byte of current touch frame to "FPD i2c"
   F. FPD-LINK pass the i2c signal to "Native i2c"

Hi Joe,

Register 0x23 of the 948 is reading 5Mbps BC speed( 0x23 = 0x28). We can test a higher BC rate by changing this rate to 10Mbps and then 20Mbps.

Change rate to 10Mbps by writing 0x48 to register 0x23.

Change rate to 20Mbps by writing 0x18 to register 0x23.

Please share slaeae captures in this thread not in a link.

Best Regards,

Gil Abarca

I'll test that soon, but need to say that I can't upload the .sal files to this web.

It keep showing Upload 0% and failed.

Hi Joe,

Test changing the BC rate and let me know if this worked. Can you also try dropping the file to the thread instead of uploading it? I do not need the video this has been posted in this thread already just the saleae capture.

Best Regards.

Gil Abarca

I still can't upload files to this thread

I just put files to my google drive first.

Here I try the BC channel 10M/ 20M mode.(Origin mode is 5M)

The result seems have no difference.

My SOC can only drive maximum of 375K of I2C frequency (2.7 µs/cycle).

I notice that the UB948 SCL frequency is about 77K (13 µs/cycle).

I modify the 0x26/0x27 of UB948 to 0x10, trying to shorten the SCL cycle.

Looks like this solves my question.

No size specified (using byte-data access)
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 58 04 00 f8 fe 1e 00 18 54 ac 00 00 00 00 00 00    X?.???.?T?......
10: 54 ac 00 00 00 00 00 00 00 01 00 00 03 19 99 09    T?.......?..????
20: 00 00 40 08 08 00 10 10 01 00 00 00 00 00 00 00    ..@??.???.......
30: 00 00 90 25 02 00 00 9a 00 00 00 00 20 e0 23 00    ..?%?..?.... ?#.
40: 43 03 03 00 60 88 00 00 0f 62 00 08 00 00 63 00    C??.`?..?b.?..c.
50: 03 10 00 01 80 00 08 00 00 7f 20 20 18 00 00 00    ??.??.?..?  ?...
60: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00    ....?...........
70: 00 00 00 07 07 08 00 00 00 00 00 00 02 00 00 00    ...???......?...
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 84 00 00 00 00 00 00 00 00 00 00 00 00 00    ..?.............
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00    ........?.......
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
f0: 5f 55 42 39 34 38 00 00 00 00 00 00 00 00 00 00    _UB948..........

Let me know if this is the valid modifications.

Or you recommend to use others way?

Additional, these regs set to 0x25~0x10, gets the same result.

Looks like the min cycle time is 4 µs.