DS90CF364A: Cycle-to-cycle jitter tolerance

Hi Kondo,

In the datasheet there is a specification that the total Receiver Skew Margin should be <750 ps at 25 MHz, and <500 ps at 65 MHz. Since this is a much older device we don't have a precise calculation for what the jitter tolerance will be for your specific frequency (31.5 MHz).

If your total system RSKM meets the specs it should work. And the system needs to meet the 250 ps jitter requirement as well.

Best regards,
Ikram

Hi Ikram

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/811043/ds90cf386-inquiry-about-ds90cf386-jitter-specification

Q1 above states that the range of clock jitter depends on frequency. However, there are no specific figures.

For example, can we estimate the following?

At 65MHz, maximum pixel clock:

Bit time = (1/(65E6*7)) = 2.198ns

Maximum clock jitter = 250ps

250ps/2198ps = 0.1137

This means that jitter can be tolerated up to 11.37% of bit time.

At 31.5MHz pixel clock:

Bit time = (1/(31.5E6*7)) = 4.535ns

Maximum clock jitter = 4535ps*0.1137 = 515ps

So, if the clock frequency is 31.5 MHz, jitter is estimated to be tolerable up to 515 ps.

Best Regards,

Kondo

Hi Kondo,

I saw the post you linked. We currently don't have an estimate or exact calculation for this. The specification in the datasheet is what the system was validated for and what we require for the system.

Best regards,
Ikram

Hi Ikram

For our system at 31.5 MHz, the minimum RSKM is 720 ps, which we believe is sufficient margin for clock jitter. In fact, it works without any problem. I have read the application notes(SNLA050) and think I understand the impact of clock jitter on data readings. What is the concern if RSKM is sufficient but clock jitter exceeds 250 ps?

You mentioned that you cannot calculate this because it is an old device, but the status of this device is "active". It is hard to believe that there is no data to calculate. For example, do you have any data on jitter at 25 MHz?

I know this may seem persistent, but I would appreciate a little more support.

Best regards,

Kondo

Hi Kondo,

You are correct, that the specification is for the RSKM and not the clock jitter. We are trying to figure out what the minimum RSKM would be for your specific frequency. I will discuss this further with my team and get back to you by Tuesday. Also, which pin are you measuring the clock jitter? 

Regards,
Ikram

Hi Ikram

Thank you so much for your response.

The measurement point is the termination resistor mounted in front of the IC. Please refer to the attached image.

Just to be clear again, what I want to know is how much clock jitter is acceptable at a frequency of 31.5 MHz.

Best regards,

Kondo

Hi Kondo,

I spoke to the team and the only recommendation for clock jitter we have is that it should be < 250 ps for any frequency up to 65 MHz. And also to make sure the RSKM meets the datasheet criteria.

Best regards,
Ikram