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DS320PR1601: GEN 5.0 REDRIVER

SHEKHA SHOUKATH
Intellectual 300 points
Part Number: DS320PR1601

Hi,

1.in DS320PR1601 datasheet (page23) it is specified that Rx detection  happens either by manually triggering via PD pins or via writing to respective I2C register .

Also in DS320PR1601 EVM user manual it is specified that all PD  pins for all channels has to be GND to enable all channels and for x16 lane application. Will it differ if the output side is 4x4 ports?

How this pin is manually triggered?

is the respective I2C register is PD override register or Rx detect control register?

could you please tell how the above two registers has to be used?

2.Are the registers General register,Device ID0 register, Device ID1 register, common for all channels?

if so then to read above registers do we need send to particular channel address, can't we read the whole retimer using a single slave address?

3.

In the programming guide  table 2-4, channel register base address is specified, but there up to channel 7 is specified. How can we access other channels upto 15.

Also by broadcast write channel bank 0 and 1(0x80), will 16 channels on A and B side be written?

How to decide the CTLE index value?

In programming guide, table 4-1, flat gain of 0dB is specified for multiple CTLE index values(0,1,2,5,6,7,8,9,10,11,12,13,14,15,16,17,18).It is mentioned in the EVM user manual and DS320PR1601 datasheet flat gain of 0dB is better and the default value.

Thanks and Regards,

Shekha Shoukath

  • 0
    TI__Genius 12280 points

    Hi Shekha,

    About question 1):

    • 4x4 bifurcation still means that all 16 channels are in use, so all PD pins should be held low during normal operation
      • PD pins each control one bank of 4 channels
    • RX detection can be manually triggered on a hardware level by toggling the PD pins from low (normal operation) --> high (powerdown) --> low (normal operation again)
    • To reset RX detection through software, I believe the appropriate registers are the PD Override registers

    About question 2):

    • The Share Registers (General, Device ID, etc.) correspond to different banks inside the device, so to my knowledge they don't necessarily apply to all channels, however most of the time there is no need to modify or read them
    • If you do need to access them, it can be done through the I2C slave address that the specific bank is assigned to (e.g. 0x18, 0x19, 0x1A...)

    About question 3):

    • The device is divided into 4 internal regions, each of these regions has an address pair and controls 8 channels, and each of the addresses in the pair correspond to one bank (one bank is 4 channels)
      • See Table 1-2 and Table 1-3 for an illustration of how the device is organized 
      • Table 2-4 shows what registers are owned by one internal region, so you can see that it has two banks numbered 0 and 1 and eight channels numbered 0-7
      • But the channel numbering in the table does not correspond to the channel numbering of the overall device, which has 32 channels
      • So I need to look at different addresses contained in different address pairs to get a full picture of the device
    • I believe broadcast writes are only performed and only apply within a single address pair at a time, so to write all channels in the device (A and B), the broadcast writes to bank 0 and 1 would need to be repeated for all four address pairs in the device
    • CTLE index values are mainly decided by manual tuning, it is difficult to say ahead of time what value will satisfy the performance and signal quality requirements of an end application
      • Refer to this application note for a detailed design procedure: (https://www.ti.com/lit/an/snla433/snla433.pdf)
      • A basic method could be to start with the Default CTLE index (boost effects are between EQ 4 and EQ 5) and examine if the system performance is satisfactory. If not, start tuning upwards (5 --> 6) and downwards (4 --> 3) to see in which direction performance improves, continue until it is successful.
    • Table 4-1 in the programming guide is a reference for how different combinations of EQ and Gain settings can be programmed into channel register offsets of 0x01 and 0x03
      • You can see that the CTLE index is controlled by offset 0x01 and the DC Gain is controlled by offset 0x03
      • In most applications it is fine to leave the DC Gain at the default value of 0 dB and focus on tuning the EQ index

    It can be difficult to understand and tune the device from the raw I2C register interface, so I would recommend using our SigCon Architect software with the DS320PR1601 profile if your application allows. It provides a GUI to conveniently read the device status, understand the layout, and adjust the settings using an external computer. Once a satisfactory device configuration is achieved, you could refer back to the programming guide to determine what sequence of raw I2C writes are needed for in-system configuration. Let us know if you have other questions.

    Best,

    Evan Su

  • 0 in reply to Evan Su
    Intellectual 300 points

    Hi,

    Thanks for the reply.

    Could you please provide some clarification on the following:

    a) for x2 lane MCIO connector sideband signals to be routed are REFCLK+, REFCLK-, PRSNT, PCIe reset  , SMCLK, SMDAT, is this correct?

    b) how signals are bifurcated in BIOS, do they follow any ordering?

    Regards,

    Shekha Shoukath

  • 0 in reply to SHEKHA SHOUKATH
    TI__Genius 14631 points

    Linking this thread as reference, as the refer to the same questions: https://e2e.ti.com/support/interface-group/interface/f/138/t/1282113 

  • 0 in reply to David Waier
    Intellectual 300 points

    Hi,

    In DS320PR1601EVM design file, for x16 PCIe slot, pins B14,B15,B19,B20  etc and A16,A17,A21,A22 etc are marked as RXp0,RXn0, RXp1,RXn1 and TXp0,TXn0, TXp1,TXn1 respecitvely.

    But in actual x16 PCIe slot B14,B15,B19,B20  etc and A16,A17,A21,A22 etc are marked asTXp0,TXn0, TXp1,TXn1 and  RXp0,RXn0, RXp1,RXn1 respecitvely (http://www.interfacebus.com/Design_PCI_Express_16x_PinOut.html).

    why the said pins are named so in PCIe edge connector and straddle connector?

    Thanks and Regards,

    Shekha Shoukath

  • 0 in reply to SHEKHA SHOUKATH
    TI__Genius 14631 points

    Hi Shekha,

    I have replied to your inquiry via this thread:https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1282113/ds320pr1601rscevm-ds320pr1601rscevm 

    Please kindly refrain from posting the same question under multiple threads. If you feel your question requires a new topic, please create a new thread to post the inquiry.

    Best,
    David