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Original question:

DS25BR110: 2 pcs of DS25BR110 cascade

DS110DF410: Cascading Retimers

Matthew Nordeen
Prodigy 70 points
Part Number: DS110DF410

Are there any issues that can occur with 3 retimer devices back-to-back-to-back (i.e. placed very close to each other in series)?  Background: For manufacturing test of our production module, we’ve designed a test board/fixture that has a retimer to help ensure that the signal amplitude going into the module is sufficient during a loopback test.  On the production module (i.e. Unit Under Test), there will be a retimer on the output, and another retimer on its input.  Both of these retimers are within a couple of inches of the connector that goes to the test board.  Therefore, the retimer on the test board will be receiving a signal that gets retimed/boosted on the output of the UUT, and will send the retimed/boosted signals (2nd retimer) into another retimer (3rd retimer) on the UUT.  As mentioned before, there is only a couple of inches of circuit board trace and a connector between each retimer.

  • 0
    TI__Mastermind 36443 points

    Hi Matthew,

    Just want to make sure I understand the system correctly before advising.  Could you review attached block diagram and make any adjustments as needed?  Could you also add either trace length or insertion loss estimates to the block diagram?

    Also, I'm assuming this is 10 GbE data.  Is this correct?

    GD Block Diagram.pptx

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 70 points

    Drew,

    Thanks for looking into this. I updated the file with the trace lengths in the design.

    GD Block Diagram_MCN.pptx

    Thanks,

    Matt

  • 0 in reply to Matthew Nordeen
    TI__Mastermind 36443 points

    Hi Matt,

    Thanks for the update.  Do you know your expected insertion loss per inch and/or do you know your PCB material?

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 70 points

    Drew,

    The circuit board with the DUT is Megtron 6 while the test board is Isola 370HR.

    Thanks,

    Matt

  • 0 in reply to Matthew Nordeen
    TI__Mastermind 36443 points

    Hi Matt,

    Thanks for the information.   I'll provide an update early next week.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    TI__Mastermind 36443 points

    Hi Matt,

    Apologies for the delay on this.  I wouldn't expect any issues from doing this, although you may need for force CTLE index 0 on some of the retimers in your system since this is a low insertion loss case.

    If you have additional concerns, I'd recommend performing IBIS-AMI simulation using DS110DF410 retimer models and your channel models.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 70 points

    Hi Drew,

    Regarding forcing CTLE index 0, would I follow the register write sequence described in the datasheet below? I understand that an Index of 0 corresponds to a 0x40 register value of 0000 per Table 11, but what value would get plugged into the other registers mentioned in these instructions?

    To manually override the CTLE boost under all conditions, perform the following steps.
    1. Set the DS110DF410 channel adapt mode to 0 by writing 0x0 to bits 6:5 of channel register 0x31.
    2. Set the desired CTLE boost setting in register 0x3a. If the DS110DF410 loses lock and attempts to lock to a
    lower data rate, it will use this CTLE boost setting.
    3. Set the desired CTLE boost setting in register 0x03.
    4. Set the desired CTLE boost setting in register 0x40.
    5. If desired, set the CTLE stage 3 limiting bit, bit 2 of register 0x13.

    Finally, a general question about this device: The device indicates an operating range of -40C to +85C, but will we need to do manual periodic re-adapts if we have to operate through the entire temperature range without a power cycle?

    Thanks,

    Matt

  • +1 in reply to Matthew Nordeen
    TI__Mastermind 36443 points

    Hi Matt,

    The value that gets plugged into the manual override registers will be the value of CTLE_STAGE[7:0] as shown in Table 11.

    For example, if you wanted to set CTLE index 16, you would write 8'b10001000 (0x80) to registers 0x3A, 0x03, and 0x40.

    Regarding operating the device over temperature, since the channels are relatively short, I think that it's less likely that you would need to change CTLE over temperature.  However, please note that the device has a "Temperature lock range" of 90C.  This means that the device is expected to be able to maintain CDR lock over +/-90C of temperature change from the original temperature where it gained CDR lock.

    Since the operating temperature of the device spans 125C, it's expected that if temperature is swept over the entire range, the device may lose CDR lock.  After losing CDR lock, it will re-lock to the data, but this will cause a temporary interruption in data.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 70 points

    Drew, I think I understand.  So, if the temperature where it gained CDR lock is -40C, it would only be expected to maintain lock between -40C and +50C, correct?

    Thanks,

    Matt

  • +1 in reply to Matthew Nordeen
    TI__Mastermind 19235 points

    That's correct. 

    Regards,

    Rodrigo Natal