Other Parts Discussed in Thread: TXU0104
Hi,
My customer is designing their board with Sitara AM62x and DP83867IR.
In their schematics, PHY nRESET_N signal is driven by AM62x PORz_OUT signal with TXU0104 (3.3V to 1.8V level shifter) in between.
Please see slide#1 in attachment.
PHY reset.pptx
Processor team (schematics review team) recommended to insert AND logic with pull down on nRESET_n signal as slide#2.
According to "DP83867 schematic and layout checklist" linked at section 3.2 in below document,
https://www.ti.com/jp/lit/an/snla246b/snla246b.pdf
"Pin Wise Checklist", Line#18 says there is an internal pull-up at RESET_n pin.
So adding an external pull-down seems not good idea.
3107.SLVRBN1_ DP83867_Design_Review_Checklist.xlsx
What is your recommendation for nRESET_N?
Thanks and regards,
Koichiro Tashiro