DP83822I: DP83822I and am572x

Rasty Slutsker

Expert 1830 points

Part Number: DP83822I

Hi,

We replaced PHY (was microchip) to DP83822HFRHBR.

The idea was drop-in replacement keep RGMII/MDIO exactly as in reference design.

It worked out of the box, but later we found a stange thing, 7% frame loss (tested with ping -f).

It appears that missing pull/up sets PHY not to rgmii mode (register 0x17 reads 0x49). When I write value 0x249 to register 0x17, communication is completely lost.

Some check with Wireshark suggest following

a) incorrect settings in 0x17 (value 0x49), some TX frames are lost

b) "correct" settings in 0x17 (value 0x249), all RX frames are lost

I cannot explain why incorrect settings work (even with 7% frame loss)! I'd expect 100% frame loss, while correct settings either trough registers or patched pull down/up brake it completely.

Thanks

rasty

over 1 year ago

+1 Hillman Lin over 1 year ago

TI__Mastermind 25955 points

Hi Rasty,

Thank you for sharing the information. I would like to ask couple questions for further debug:

May I ask what is your setup? A block diagram would be helpful
If possible, could you share me the register read 0x0467?
Could you also write 0x0017 to 1249 to see if that solve the issue.

Thank you,

Hillman Lin

0 Rasty Slutsker over 1 year ago in reply to Hillman Lin

Expert 1830 points

Than you very much for the answer.

0x467 is 0x2001.

0x468 is 0x5006

0x469 is 0

Writing 0x1249 to 0x17 did some majic! Ethernet is back to life. But stress test under linux is still not 100% stable.

Questions:

1. Why RGMII kind of "works" even if 0x17 reads 0x49?

2. why do you immidiatey suggest RX clock shift? What else should we know? Some PCB routing constrains?

Side notes:

1. Under linux phytool cannot read PHY registers above 0x20, it returns garbage.

2. Under linux 2 identical PHYs connected to 2 ports of GMAC behave differently, the only difference is MDIO address (strap).

3. Under Linux port 0 works without delay, 0x17 reads 0x249, while port 1 requirs delay,

Thansk a lot!

Rasty

0 Hillman Lin over 1 year ago in reply to Rasty Slutsker

TI__Mastermind 25955 points

Hi Rasty,

Glad that it works on in your case. I think RGMII can still have some communication even when 0x17 is 49. However, the MAC communication is in 100mbps therefore you will see some packets error or packets loss.

RX clock shift is always a recommendation for RGMII communication.

Regarding to not able to reading PHY register above 0x0020, it seems like you an extended register reading issue. Could you take a look at the following FAQ to see if that help if your current situation:

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1271487/faq-extended-register-space-access-for-ethernet-phys?tisearch=e2e-sitesearch&keymatch=extended%20register#

Thank you,

Hillman Lin

0 Rasty Slutsker over 1 year ago in reply to Hillman Lin

Expert 1830 points

working setup

port 0 register 0x17 is set to 0x249

port 1 register 0x17 is set to 0x1249

0 Hillman Lin over 1 year ago in reply to Rasty Slutsker

TI__Mastermind 25955 points

Hi Rasty,

Glad that it work out for you. Thank you for the update.

Regards,

Hillman Lin

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DP83822I: DP83822I and am572x