TCAN4550-Q1: Tx Buffer request Pending status

Hi Mingkang,

Mingkang Song said:

The can transmit status is monitored by reading the "Tx Buffer request Pending" register. According to the chip manual, 0 is defined as "No transmission request pending", 1 is "Transmission request pending", but we have a third state in the project measured 2. Please help confirm: what state is the TCAN 4550-q1 chip in this state? Why is this happening?

Each bit of the TX Buffer Request Pending (TXBRP) register is associated with its own TX Buffer.  You can configure up to 32 TX Buffers that are indexed with a buffer ID number of 0-31.  Therefore, bit 0 of the TXBRP register will return status for TX Buffer 0.  Likewise bit 1 will return the status for TX Buffer 1.

When you read the TXBRP register as a whole, and you get the value of 2, this simply means that TX Buffer 1 has a transmission request pending which simply means that the device is trying to send a message from TX Buffer 1 that has not been completed yet.

If you were to read the TXBRP register and get the value 3, this would me that you have messages pending transmission in both TX Buffer 0 and TX Buffer 1.

Mingkang Song said:

Also, what is the minimum write cycle for the TCAN4550-Q1 chip?

I think you are referring to the minimum time between CAN message transmissions, or how fast the TCAN4550 can transmit CAN messages.  Is this correct?

All communication with the TCAN4550 is done through the SPI bus interface, therefore the SPI data rate and efficiency will be the primary factor that determines the minimum cycle time.  But the CAN protocol and arbitration can also impact the time needed to transmit a message.

Once a message is loaded to the TX Buffer element, the corresponding bit in the TX Buffer Add Request (TXBAR) register should be set to 1.  This will start the transmission process and the device will set the corresponding bit in the TXBRP register and try to transmit the message on the CAN bus following the arbitration protocol.  Once the message has been transmitted, the device will clear the TXBRP bit and set the corresponding bit in the TX Buffer Add Request Transmission Occurred (TXBTO) register that can be monitored to determine if the transmission was successful.  The TXBTO register will retain this status until a new message is transmitted from that register and the corresponding TXBRP bit gets set back to 1.

The device does not clear the message data in the TX Buffer elements automatically after a transmission, so it is possible to repeatedly transmit the same message if you desired.  You would simply need to set the TXBAR bit to 1 again for that buffer to start another transmission.  Therefore the minimum cycle time for transmitting the same message would be determined by how long it took the SPI to set the TXBAR register following the TXBTO showing the previous transmission occurred.

Mingkang Song said:

If it can not write, what is the register value of TX buffer, Tx Buffer request Pending?

The TX buffer element is just a memory area that will hold the contents of the message to be transmitted and it doesn't self-clear.  Therefore the MCU determines what the contents of the TX Buffer are.

The TX Buffer Request Pending register will reflect of status of any TX Buffers that have had a transmission initiated by setting the TXBAR bit to 1.  The TXBRP register bit will be 1 for any TX Buffers that have not yet successfully transmitted the message.  Once the message has been transmitted, the TXBRP bit will be set to 0.  It is possible to cancel a message transmission through the TX Buffer Cancellation Request (TXBCR) register and this will stop the the transmission and clear the TXBRP bit.

The TCAN4550-Q1 uses the CAN FD Controller IP called M_CAN developed by Bosch.  I would recommend you read the M_CAN User's Manual for more detailed information on the MCAN registers. (Link)

You can treat this MCAN User's Manual as a supplemental document to the TCAN4550-Q1 datasheet and the TCAN455x Software User's Guide (Link).  The only difference I need to point out is that the TCAN4550-Q1 has added an offset of 0x1000 to each of the MCAN registers.  Therefore the TXBRP register in the MCAN User's Manual is 0xCC, but the TCAN4550 register address is 0x10CC. 

Regards,

Jonathan