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DS90UB940-Q1: Help with 0x6c/6d indirect register setting

Wei Xiao
Intellectual 445 points
Part Number: DS90UB940-Q1

We are using UB940 pairing with UB947. While we can get normal image from one video source, another one has no display at all. We suspect that we need to change  0x6c/6d indirect register values in order to make it work. Here are the information we got for the input image. Please help us set the correct values for  0x6c/6d indirect registers.

horizontal front porch: 25 pixels

horizontal sync pulse: 3 pixels

horizontal back porch: 32 pixels

horizontal active: 800 pixels

horizontal total: 860 pixels

vertical front porch: 17 lines

vertical sync pulse: 4 lines

vertical back porch: 5 lines

vertical active: 487 lines

vertical total: 513 lines

frames per second: 60

  • 0
    TI__Mastermind 21500 points

    Hi Wei,

    So lock signal looks ok between Ser and Des? Only difference is timing?

    If that's the case please refer to ticket here - Link 

    This is the Appnote - How to Configure DS90UH940N-Q1 MIPI ® D-PHY Timing Parameters

    Regards,
    Fadi A.

  • 0 in reply to Fadi Abdulhameed
    Intellectual 445 points

    Hi Fadi,

    Thank you for the information. The upstream video source is fixed. We have no control over that. With the info you provided, I am still unclear on how to go from the parameters we obtained for the video source to getting correct CSI I/F register settings. Is there another source you can point me to calculating MIPI timing parameters from the ten parameters we have for the video source? Thanks.

  • 0 in reply to Fadi Abdulhameed
    Intellectual 445 points

    Based on the following post, I thought you can provide the register settings for the video parameters I mentioned.

    e2e.ti.com/.../ds90ub940-q1-how-to-configure-the-csi-indirect-register-of-0x02

  • 0 in reply to Wei Xiao
    TI__Mastermind 21500 points

    Hey Wei,

    Let me review and get back to you by tomorrow 1/30

    Regards,
    Fadi A.

  • 0 in reply to Fadi Abdulhameed
    TI__Mastermind 21500 points

    Hey Wei,

    Your PCLK is 26 Mhz which correlates to the following:

    So you'd need to run the following code:

    WriteI2C (0x6C, 0x00) // Set register offset for CSI_TCK_PREP
    WriteI2C (0x6D, 0x82) // Set register value for CSI_TCK_PREP
    WriteI2C (0x6C, 0x01) // Set register offset for CSI_TCK_ZERO
    WriteI2C (0x6D, 0x88) // Set register value for CSI_TCK_ZERO
    WriteI2C (0x6C, 0x02) // Set register offset for CSI_TCK_TRAIL
    WriteI2C (0x6D, 0x84) // Set register value for CSI_TCK_TRAIL
    WriteI2C (0x6C, 0x03) // Set register offset for CSI_TCK_POST
    WriteI2C (0x6D, 0x92) // Set register value for CSI_TCK_POST
    WriteI2C (0x6C, 0x04) // Set register offset for CSI_THS_PREP
    WriteI2C (0x6D, 0x82) // Set register value for CSI_THS_PREP
    WriteI2C (0x6C, 0x05) // Set register offset for CSI_THS_ZERO
    WriteI2C (0x6D, 0x84) // Set register value for CSI_THS_ZERO
    WriteI2C (0x6C, 0x06) // Set register offset for CSI_THS_TRAIL
    WriteI2C (0x6D, 0x84) // Set register value for CSI_THS_TRAIL
    WriteI2C (0x6C, 0x07) // Set register offset for CSI_THS_EXIT
    WriteI2C (0x6D, 0x86) // Set register value for CSI_THS_EXIT
    WriteI2C (0x6C, 0x08) // Set register offset for CSI_TLPX
    WriteI2C (0x6D, 0x82) // Set register value for CSI_TLPX

    Regards,
    Fadi A.

  • 0 in reply to Fadi Abdulhameed
    Intellectual 445 points

    Hi Fadi,

    Thank you for the reply. It seems that you just calculated the PCLK and then use Recommended Parameter Settings from snla303 document. So, the setting has nothing to do with the values of front porch, back porch, etc? If that's the case, why would Mr. Shi ask for those in the post I mentioned if he only needs htotal and vtotal and frame rate?

  • 0 in reply to Wei Xiao
    TI__Mastermind 21500 points

    Hi Wei,

    Did this script not work for you? I don't see anywhere where you could program the timing, the only thing that could be programmed is based on the PCLK frequency. 

    Regards,
    Fadi A.