TFP401: Unable to get proper video output on TFP401PZP,Ghost screen & distorted pixels

Hey Arjit,

looking into this now, will get back to you as soon as I can.

Yes Sir please guide me in any possible way.

Waiting for your response.

settings mean:

DFO = continuous clock

nPDO = normal operation/ drivers on

ST = high drive strength

PIXS = 1px/clk

nSTAG = should be irrelevant for 1 px mode, but try setting to simultaneous

OCK_INV = rising edge, tru checking the falling edge trigger

Can you take a look at the output clock, VSYNC, and HSYNC from the TFP401 on an oscilloscope? Is there anything amiss with these signals or do they look stable?

Additionally can you share layout files?

Hello Sir

As I mentioned above my board pin configurations as follow:

DFO = pulled down for continuous clock

nPDO =connected to SCDT for normal operation/ drivers on

ST = pulled up for high drive strength

PIXS = pulled down for  1px/clk

nSTAG = pulled high for Normal simultaneous even/odd pixel output

OCK_INV = pulled high for : Latches output data on rising ODCK edge

My findings through oscillopscope:

ODCK=48-51MHz 

VSYNC=37.43KHz

HSYNC=37.37KHz

Below attching both pdf & design file of board layout(Only relevant section inculded):

DISPLAY REVIEW.pdf

Layout: 1106.Display Driver Board PCB Layout.zip

Hey Arijit,

Ill have a look at the layout and schematic, but did you also try falling edge trigger for the ODCK_INV?

A few things,

1) It seems that you connected all the 3.3V pins on the same net going across one set of ferrite beads. The proper implementation is below, not properly isolating the different voltage supplies will cause major power supply noise on the PLL and the core. Proper references can be seen in section 10 and 11 of the datasheet.

2) I am unable to open your layout file due to its format. Can you send a .brd file?

3) based off of the layout images sent, it doesn't seem that the traces are properly length matched. Diff pairs' length should be ~2mils or less apart. 

4) additionally it seems that there is improper ground layer coupling through vias on this board. See figure 12.3 on the datasheet.

Let me know if you have any more questions

Best,

Vishesh Pithadiya

Sir,

All of the differential pair lengths are less than 2" and equally lengthed/tuned correctly because I also followed the same design note while designing the PCB. I don't have Altium Designer, so I am unable to provide the PCB file you requested.

Also tried falling edge trigger for ODCK_INV as well, but the outcome was the same.

Is there a problem with the EDID programming or something else?

• Note: I've followed Waveshare's 7-inch HDMI display board's PCB layout which is pretty much similar to my design(both layout & Schema).
• If you need more information I can mail you.

Thank you,Have a nice day Sir

Hey Arijit,

We use e2e as a sole means for communication for tracking purposes. Upon looking at the panel datasheet, you are looking to output to a 480 by 800 display meaning that your HSYNC and VSYNC timing should not be the same. Additionally your ODCK frequency is 48-51 MHz which is outside of the spec of your panel:

Please double check your source settings, as the ODCK, HSYNC, and HSYNC seem to be incorrect.

Hello, Sir

Just let me know one thing.I have an old display driver board that uses TFP401APZP IC But I have TFP401PZP .Everything works perfectly and the display works flawlessly when I connect the same LCD panel to the old driver board; however,above issue appears when I connect the display to my newly designed driver board.

Left image: Same LCD with TFP401APZP  IC on old driver board.

Right image: Same LCD with TFP401PZP IC on new driver board.

Are these two IC significantly different from one another or is there anything I'm missing out?

Thank You

Hey Arijit, 

The only difference between the TFP401 & TFP401A is that the TFP401A includes HSYNC regeneration circuitry. This was required to be interoperable with the Sil154 that exhibited HSYNC jitter. However, the Sil154 is no longer on the market. They are pin to pin compatible. Can you have a look at the HSYNC, VSYNC, and OSCK timings for the working display.

I think that the clock, HSYNC, and VSYNC timings will be different on the working vs. not working display.

Alright sir.I will retest the circuit and report back to you.What is the expected timing of those signals? and What else could be causing the video output to seem this way?

Here are some general relationships that you should see between HSYNC, VSYNC, and ODCK: 

ODCK/ H_total = HSYNC freq

ODCK/ (H_total * V_total) = VSYNC freq

VSYNC freq = panel refresh rate

Hello sir,

I have tested the circuit of both old and new driver board through Oscilloscope. 

My findings through oscillopscope:

Old driver board:

ODCK=49MHz

DE=35.91KHz(VPP=2.43V)

HSYNC=37.34KHz

VSYNC=60Hz

New driver board:

ODCK=34MHz

DE=28.81KHz(VPP=2.27V)

HSYNC=31.04KHz

VSYNC=60Hz

The only issue with new driver board is that the clock, HSYNC, and VSYNC timings dissapear after few minutes(5min) of display on time.

Till 5 mins display stays in dark mode with some vertical lines after 5 mins display output transforms to the image posted above.

From my end it looks like you've set everything up correctly.

Have you already tried using another chip? Also double check the output terminations on the LVDS side.  From my understanding the waveforms look normal, but go away after 5 minutes, correct?

What changed between the original waveforms and now?

Yes sir I replaced the old IC with a new one and also the oscilloscope probe was defective. After changing the probe I got exact readings.Aslo checked the output terminations on the LVDS side and no problem in it.

Edit:After turning off the screen blanking option in source computer the black screen didn't disappear.Now the only problem is tthe display remains in black screen mode.

How can I ensure whether the IC is de-serializing TMDS inputs into parallel bits or not ? Is there any thing should I test?

#Troubleshooting steps

 It seems that the hardware is implemented correctly, but the video timings are off:

These calculations are done under the assumption that the panel is the same for both devices. The old board (working) is already out of spec of the display panel as max DCLK is 46.8 MHz but its working which doesn't make sense. The new board is actually implementing closer to the correct timings, but isn't working. 

Am I missing something?

I think the old driver has 1024x800 resolution display connected to it.(datasheet not found)Whenever I connect the new display to the old driver board I change the resolution in EDID and connect.

I've tried connecting both old and new display to my newly designed board but none of them worked, but they work good in old driver board.

Hmmm ok, the timing measurements that you sent for the old board and new board are for the 800x480 correct?

Actually I forgot to mention that If I connect 800x480 display to both driver board the timings are acuurate.

i.e 

ODCK=34MHz

DE=28.81KHz(VPP=2.27V)

HSYNC=31.04KHz

VSYNC=60Hz

In case of 1024x600 display, when I connect to both driver board

ODCK=49MHz

DE=35.91KHz(VPP=2.43V)

HSYNC=37.34KHz

VSYNC=60Hz

The only issue is that I can get video output in old driver board using both display but not with the new board.

Try setting the DFO pin from 0 ->1 

Also probe the SCDT pin to see if the device sees the lanes operating properly

Also what's the Vpp you measure coming out of the TFP401A? It seems that the panel is expecting 4V

If you have the soldering equipment available, could you solder the TFP401 onto the new board and the TFP401A onto the old board. This will help identify if the chip is not cooperating or if the board is the issue.

Setting DFO to activate high will bring no change because I have TFT support panel.(already tried)

I've tested the SCDT pin it remains high until the ODCK/DE runs continuously.

As I said before panel has different power supply unit for both backlight and lcd driver circuit.Power distribution is perfectly done.

IC replacement is the only option left for me. Apart from it ,is there any thing that I should try?

Ill look into other options, but it seems like we have already covered all our bases. Let me know if swapping the chips changes anything,

I swapped the ICs put the TFP401PZP on working board and TFP401APZP on non working board. The old board worked on TFP401PZP Ic but the new board still showing same issue.One thing I learned that problem was not with ICs.

Still have a look on this timings diagram.

Old display Column-1024x600 panel on working board

New display column- 800x480 panel on non working board

Everything is identical but still couldn't figure out what is the issue.

Like I mentioned earlier, if this issue doesn't follow the chip, it means that the layout/ schematic implementation was incorrect. What did you do different between the two boards? In terms of schematic and layout

Only difference is old board includes 90ohm common mode choke near differential pair where new board doesn't also smaller in size, apart from it every thing is identical

Is there any way you can check the EMI on the new board? If this is the only difference between the working board and the new board, this is the only explainable issue.

Yes, I have the same thoughts. Could there be an EMI issue on the HDMI output or input side? I have doubt on diff. Pair routing.What do you think?

If the issue is stemming from the board like we confirmed it most likely is a trace/ layout problem. Is there any chance there was an issue in fabrication? Unfortunately there isn't much I can do on our end to further support, but let me know if you have any questions in debug.

Hey Arijit,

I'm closing this thread due to inactivity.