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Original question:

DP83822I: COL behavior at reset deassert

DP83822I: Reason why VDDIO was detected as 2.5V

Go
Genius 4190 points
Part Number: DP83822I

Hi, David

I'm really sorry for late answer to the related thread.

Regarding your advice in previous thread below,

>Register 0x421 is showing that VDDIO was detected as 2.5V. We can force the detection to 3.3V using register 0x41F bits[11:10]. Please try this and issue a soft reset afterwards 0x001F = 0x4000. 

The customer force the detection to 3.3V, then the failure case seems to be fixed.

Do you have any idea that call to mind why register 0x421 is set VDDIO to be detected as 2.5V even though the VDDIO is 3.3V? 

Thanks,

Go

  • 0
    TI__Mastermind 31755 points

    Hi Go,

    I can handle this thread from David. We have seen this behavior mostly due to power supply sequence. However, this is why we do have register configuration to rectify this behavior.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Genius 4190 points

    Hi, Gerome

    Thank you for your comment, let me ask you a little more detail.

    What does "due to power supply sequence" mean? 

    Customer may have some violation with 7.6 Timing Requirements, Power-Up Timing in customer situation? 

    when and how does DP83822I set the bit 1:0 of Register 0x421 in Figure 7-1. Power-Up Timing?

    Thanks,

    Go 

  • 0 in reply to Go
    TI__Mastermind 31755 points

    Hi Go,

    I cannot provide more information outside of footnote 3 on page 12 of SNLS505G.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Genius 4190 points

    HI, Gerome

    Thank you for your comment.

    Regarding the footnote 3 on page 12 of SNLS505G below,

    " AVD ramping up after VDDIO ramp completion is preferred to avoid false detection of lower level of VDDIO in any corner case."

    Does the situation below also have possibility to false detection of lower level of VDDIO?

    (Situation )
    AVD and ADDIO ramp up simultaneously , after the ramp completion of them, then Hardware RESET_N is de-asserted.

    I'd like to know RESET_N de-assert timing will affect the occurrence of false detection of lower level of VDDIO or not.

    Thanks,

    Go

  • 0 in reply to Go
    TI__Mastermind 31755 points

    Hi Go,

    We have not seen this situation occurring, but we do have provisions to force the VDDIO to 3.3V if in case. Do you see if changing when Reset is deasserted at a different point in time?

    Sincerely,

    Gerome