DP83848I: CPU and Ethernet PHY cannot communicate.

Hiroaki Yuyama TED

Part Number: DP83848I

Dear, TI Support Team.

Our customer is evaluating the DP83848IVV and is unable to communicate.

Model: DP83848IVV/NOPB
Communication: MII
Address: 00111

The symptom is that the CPU and Ethernet PHY cannot communicate.

When doing Register Read, PHY should output Low, but it remains High.
I am inputting a 25MHz clock to X1, but it is not output from CLK_OUT.
The data sheet says that 25MHz is output during MII communication. It remains Low.

Attached are waveforms and circuit diagrams during MDC and MDIO communication.

DP83848I Waveform during MDC, MDIO communication.pptx
Best Regards,
Hiroaki Yuyama

8 months ago

0 Gerome Cacho 8 months ago

TI__Mastermind 32455 points

Hello,

Can customer please fill out this schematic checklist to assist in moving forward with debug?

7220.DP83848_Schematic_Design_Review_Checklist.xlsx

Sincerely,

Gerome

0 Hiroaki Yuyama TED 8 months ago in reply to Gerome Cacho

Expert 1430 points

Hi,Gerome-san.
Thank you for your advice.

We have already sent the Excel file to the customer.
Customers are in a hurry to resolve their issues.
so if you are a my ti user, you will be replying to the E2E Design support Interface forum directly from the customer.

Best Regards,
Hiroaki Yuyama

0 Gerome Cacho 8 months ago in reply to Hiroaki Yuyama TED

TI__Mastermind 32455 points

Hello,

Thank you for the update. I will await their response.

Sincerely,

Gerome

0 Hiroaki Yuyama TED 8 months ago in reply to Gerome Cacho

Expert 1430 points

Hello Gerome-san.

We received a reply from the customer.

The customer worked fine.

The cause was a hardware connection error and the Power Feedback Connection was not designed correctly.

The customer had a connection error in datasheet item 7.2.1.3 Power Feedback.
To ensure correct operation for the DP83848I, parallel caps with values of 10 µF and 0.1 µF should be placed close to pin 23 (PFBOUT) of the device. Pin 18 (PFBIN1), pin 37 (PFBIN2), pin 23 (PFBIN3) and pin 54 (PFBIN4) must be connected to pin 31 (PFBOUT), each pin requires a small capacitor (.1 µF). See Figure 7-4 below for proper connections.

Best Regards,
Hiroaki Yuyama