DP83867CR: MDIO port configuration

Hi Mochizuki,

Thank you for sharing your observation. 

May I ask what is bias voltage you are mentioning earlier? Is the bias voltage the during H-Z stage?

Are you connected to another SoC when you are measuring the MDIO line? 

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Regards,

Hillman Lin

Hi Lin,

Oh! I missed to attach a file.

Here is MDIO pin monitor waveform at OPEN condition, no other external connection.

We can see 3 state voltage output even no PU resistor or SOC connection.

Regards,

Mochizuki 

Hi Mochi,

Thank you for sharing the waveform. I will discuss with the team and provide you an response.

Meanwhile, may I ask are you facing any MDIO/MDC communication issue?

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Regards,

Hillman Lin

Hi Lin,

No, we are not facing MDIO/MDC communication issue, but just proceeding verification of each pin function.
Then there is discrepancy of the voltage waveform from expected I/O pin configuration, open drain.

Regards,

Mochizuki

Hello Lin,

We understood to get full functionality external PU resister is needed.

Is it possible to know why actual device has 3state output voltage even no PU resistor for open drain port?

Regards,

Mochizuki  

Hi Mochizuki,

For our understanding, you are seeing an 3-stage voltage in your MDIO signal because you are missing a pull up on the MDIO line. There is some internal structure inside the MDIO pin and result in an weak pull up during Hi-Z stage. In order to prevent this weak pull up in MDIO line, we always recommend to have pull up resistor on MDIO lines.

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Regards,

Hillman Lin