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Original question:

TS3DV642-Q1: Switch1 TS3DV642-Q1 and Switch2 TS3DV642-Q1 can support 4lane mode CPHY input from portA and portB， Output 4Lane...

TS3DV642-Q1: Can TS3DV642-Q1 use for 2lane mipi DPHY for camera signal transmit?

CHENG KAI
Prodigy 80 points
Part Number: TS3DV642-Q1

Hi,

As you can see below figure,I add some red block which I want to use the two lane MIPI DPHY for ramera signal,

Would you please share some information for me:

1. Can this design work well, is there any risk should be paid attention?

2. Does this design used in any Mass Production without any problem before?

3. Does Ti team have any signal test report like the hdmi1.4 complicnace at 3Gbps and 6Gbps eye diagram before and after the mux shown in spec ?

4. About the PCB route guide, do we take reference in figure 11-1？

  • 0
    TI__Guru**** 177151 points

    Hi,

    TS3DV642-Q1 can support the two lane MIPI DPHY design as you showed in your block diagram. But I am not aware of a design in a mass production and I also do not have the MIPI signal test report.

    What is your targeted data rate? Do you want to add a MIPI re-timer such as the DPHY440 at the TS3DV642-Q1 output? 

    Thanks

    David 

  • 0 in reply to David (ASIC) Liu
    Prodigy 80 points

    Hi David，

    Thanks for your answer.

    Below figure is shown in spec. It seems pretty good under 6Gbps HDMI，so can we say it will be low risk used for 2lane DPHY MIPI  without ant retimer？

  • 0 in reply to CHENG KAI
    TI__Guru**** 177151 points

    HI,

    It depends on your targeted data rate and PCB design. For the 6Gbps HDMI, the EVM I designed has total PCB trace length of 3.8in without going through any via. Since MIPI data rate will be lower than the HDMI6G, you can design the PCB trace to be longer. 

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 80 points

    hi David，

    Sound good for HDMI. Another two questions:

    1, Does this mux chip used for hdmi or other high speed inferface in mass prodution your team know?

    2, Can we have the necessary that we get the EVK board? Or from Chinese location Ti FAE?

    3, How do you think the risk for mux used for MIPI DPHY mass prodution, maybe focus on the stability. Can I get any information from your team?

    Chengkai

  • 0 in reply to CHENG KAI
    TI__Guru**** 177151 points

    Chengkai

    Please see my inserted response below

    1, Does this mux chip used for hdmi or other high speed inferface in mass prodution your team know?

    Yes

    2, Can we have the necessary that we get the EVK board? Or from Chinese location Ti FAE?

    You can order directly from ti.com, https://www.ti.com/tool/TS3DV642Q1EVM-105, or ask our local FAE in China to request an EVM for you.

    3, How do you think the risk for mux used for MIPI DPHY mass prodution, maybe focus on the stability. Can I get any information from your team?

    I do not see this as an issue, here is the link to the TS3DV642-Q1 reliability report, https://www.ti.com/quality-reliability-packaging-download/report?opn=TS3DV642RUARQ1.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 80 points

    hi David，

    Below is my sch design for TS3DV642RUARQ1，would you please help review and answer my three questions ：

    1，What is the VCC value if the 2lane MIPI CPHY voltage is 1.8V？

    2，How can I deal with the IIC interface-PIN3/4,PIN38/39/40/41，they all connect to SOC for configure，what is the pull up voltage-1.8V？Or IIC interface does not need？

    3，How can I set the mux IIC adress？

    Thanks，

    Chengkai

  • 0 in reply to CHENG KAI
    TI__Guru**** 177151 points

    Chengkai

    CHENG KAI said:
    1，What is the VCC value if the 2lane MIPI CPHY voltage is 1.8V？

    VCC is minimum of 3.0V and max of 3.6V. Typically VCC is 3.3V.

    CHENG KAI said:
    2，How can I deal with the IIC interface-PIN3/4,PIN38/39/40/41，they all connect to SOC for configure，what is the pull up voltage-1.8V？Or IIC interface does not need？

    IIC interface is to support HDMI DDC bus switching, they are not used for TS3DV642-Q1 configuration. TS3DV642-Q1 can only be configured through EN, SEL1, and SEL2 pin.

    3. The schematic itself look.

    Thanks

    David