Hello,
Our customer is evaluating LMH0341 as following signal chain.
SDI input -->LMH0344-->LMH0341-->FPGA-->LCD
Our finding is that there is very less chance but it create V sync error when SDI data is on/off around 50 times trial.
Here is question TRS (EAV, SAV) timing is re-clocked and re-inserted on LMH0341 re-serializing process?
Our customer suspect if LMH0341 does not have such a function then this type of V sync error should not be occurred.
How can we clear doubts of this inquiry?
Regards,
Mochizuki
